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Searched refs:OPENRISC_IP_2_ADDR (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DregTSP.h1193 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c2936 …IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE) || in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DregTSP.h1193 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c2940 …IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE) || in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DregTSP.h1191 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c2951 …IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE) || in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DregTSP.h1727 #define OPENRISC_IP_2_ADDR 0x90000000 macro
H A DhalTSP.c4345 …IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE) || in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h1883 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c4764 …IsCover(phyhwaddr, phyhwaddr+ u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h1903 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c4727 …IsCover(phyhwaddr, phyhwaddr+ u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h2073 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c5094 …IsCover(phyhwaddr, phyhwaddr+ u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h2078 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c5419 …IsCover(phyhwaddr, phyhwaddr+ u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h2078 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c5436 …IsCover(phyhwaddr, phyhwaddr+ u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h2070 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c5492 …IsCover(phyhwaddr, phyhwaddr+ u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE… in HAL_TSP_SetFwDbgMem()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h2070 #define OPENRISC_IP_2_ADDR 0x90000000UL macro
H A DhalTSP.c5453 …IsCover(phyhwaddr, phyhwaddr+ u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE… in HAL_TSP_SetFwDbgMem()