| /utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/ |
| H A D | regTSP.h | 1191 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 2935 …if(IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_SIZE… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/ |
| H A D | regTSP.h | 1191 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 2939 …if(IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_SIZE… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/ |
| H A D | regTSP.h | 1189 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 2950 …if(IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_SIZE… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/ |
| H A D | regTSP.h | 1725 #define OPENRISC_IP_1_ADDR 0x00200000 macro
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| H A D | halTSP.c | 4344 …if(IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_SIZE… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/ |
| H A D | regTSP.h | 1881 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 4763 …if(IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/ |
| H A D | regTSP.h | 1901 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 4726 …if(IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | regTSP.h | 2071 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 5093 …if(IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | regTSP.h | 2076 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 5418 …if(IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | regTSP.h | 2076 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 5435 …if(IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | regTSP.h | 2068 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 5491 …if(IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_… in HAL_TSP_SetFwDbgMem()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | regTSP.h | 2068 #define OPENRISC_IP_1_ADDR 0x00200000UL macro
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| H A D | halTSP.c | 5452 …if(IsCover(phyhwaddr, phyhwaddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_… in HAL_TSP_SetFwDbgMem()
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