Home
last modified time | relevance | path

Searched refs:MIU2_REG_RQ4_MASK (Results 1 – 20 of 20) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c227 #define _MaskMiu2Req_MVD_RW_RTO( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK+1, m, BIT(1))
229 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(4))
230 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(5))
231 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK+1, m, BIT(3))
271 #define _MaskMiu2Req_EVD_RW1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
272 #define _MaskMiu2Req_EVD_RW2( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(1))
273 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK+1, m, BIT(2))
274 #define _MaskMiu2Req_EVD_LITE_RW1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
275 #define _MaskMiu2Req_EVD_LITE_RW2( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
276 #define _MaskMiu2Req_EVD_LITE_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
H A DregHVD_EX.h680 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c231 #define _MaskMiu2Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
233 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
234 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
235 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(0))
265 #define _MaskMiu2Req_EVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
266 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
H A DregHVD_EX.h637 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c217 #define _MaskMiu2Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
219 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(0))
251 #define _MaskMiu2Req_EVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
252 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
H A DregHVD_EX.h638 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c232 #define _MaskMiu2Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
234 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
235 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
236 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(0))
266 #define _MaskMiu2Req_EVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
267 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
H A DregHVD_EX.h637 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c231 #define _MaskMiu2Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
233 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
234 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
235 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(0))
265 #define _MaskMiu2Req_EVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
266 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
H A DregHVD_EX.h637 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h421 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h429 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h429 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h429 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h449 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h449 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h447 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h636 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h636 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h664 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) macro