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Searched refs:MIU2_REG_RQ2_MASK (Results 1 – 20 of 20) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h419 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h427 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h427 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h427 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h447 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h447 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h445 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h634 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h635 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
H A DhalHVD_EX.c230 #define _MaskMiu2Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h635 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
H A DhalHVD_EX.c230 #define _MaskMiu2Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h636 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
H A DhalHVD_EX.c216 #define _MaskMiu2Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h634 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h635 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
H A DhalHVD_EX.c231 #define _MaskMiu2Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h678 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro
H A DhalHVD_EX.c226 #define _MaskMiu2Req_MVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(6))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h662 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) macro