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Searched refs:IRQ_REG (Results 1 – 25 of 28) sorted by relevance

12

/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
270 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
294 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
296 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h193 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr) << 2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
270 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
294 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
296 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
270 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
294 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
296 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h193 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr) << 2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
270 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
294 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
296 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
270 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
294 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
296 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalCHIP.c197 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
199 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
217 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
219 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
267 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
287 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
289 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h185 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr)<<2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalCHIP.c197 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
199 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
217 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
219 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
267 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
287 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
289 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h182 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr)<<2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalCHIP.c197 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
199 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
217 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
219 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
267 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
287 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
289 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h182 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr)<<2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalCHIP.c166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
245 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
247 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
269 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
271 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
422 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
423 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h146 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr) << 2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalCHIP.c197 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
199 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
217 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
219 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
267 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
287 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
289 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h182 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr)<<2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalCHIP.c197 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
199 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
217 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
219 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
267 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
287 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
289 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h182 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr)<<2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalCHIP.c166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
245 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
247 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
269 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
271 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
422 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
423 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h146 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr) << 2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalCHIP.c166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
245 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
247 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
269 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
271 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
422 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
423 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h146 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr) << 2)))) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalCHIP.c197 u32Reg = IRQ_REG(REG_IRQ_PENDING_H); in _CHIP_LISR0()
199 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L); in _CHIP_LISR0()
217 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H); in _CHIP_LISR0()
219 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L); in _CHIP_LISR0()
267 u32Reg = IRQ_REG(REG_FIQ_PENDING_H); in _CHIP_LISR1()
269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
287 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H); in _CHIP_LISR1()
289 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L); in _CHIP_LISR1()
439 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF; in CHIP_EnableIRQ()
440 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF; in CHIP_EnableIRQ()
[all …]
H A DregCHIP.h185 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr)<<2)))) macro

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