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Searched refs:HVD_REG_RESET (Results 1 – 25 of 68) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DhalHVD_sub.c656 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SVD_Release()
822 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SwCPURst()
826 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_Sub_SwCPURst()
1042 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_Sub_SetRegCPU()
1045 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_Sub_SetRegCPU()
1048 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1052 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1057 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1062 HVD_SUB_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_Sub_SetRegCPU()
1063 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_Sub_SetRegCPU()
[all …]
H A DhalHVD.c669 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_SVD_Release()
835 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_SwCPURst()
839 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_SwCPURst()
1088 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_SetRegCPU()
1091 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_SetRegCPU()
1094 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1098 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1103 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_SetRegCPU()
1108 HVD_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_SetRegCPU()
1109 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_SetRegCPU()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DhalHVD_sub.c656 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SVD_Release()
822 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SwCPURst()
826 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_Sub_SwCPURst()
1042 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_Sub_SetRegCPU()
1045 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_Sub_SetRegCPU()
1048 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1052 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1057 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1062 HVD_SUB_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_Sub_SetRegCPU()
1063 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_Sub_SetRegCPU()
[all …]
H A DhalHVD.c669 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_SVD_Release()
835 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_SwCPURst()
839 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_SwCPURst()
1088 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_SetRegCPU()
1091 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_SetRegCPU()
1094 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1098 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1103 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_SetRegCPU()
1108 HVD_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_SetRegCPU()
1109 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_SetRegCPU()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DhalHVD_sub.c656 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SVD_Release()
822 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SwCPURst()
826 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_Sub_SwCPURst()
1042 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_Sub_SetRegCPU()
1045 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_Sub_SetRegCPU()
1048 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1052 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1057 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1062 HVD_SUB_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_Sub_SetRegCPU()
1063 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_Sub_SetRegCPU()
[all …]
H A DhalHVD.c669 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_SVD_Release()
835 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_SwCPURst()
839 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_SwCPURst()
1088 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_SetRegCPU()
1091 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_SetRegCPU()
1094 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1098 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1103 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_SetRegCPU()
1108 HVD_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_SetRegCPU()
1109 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_SetRegCPU()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DhalHVD_sub.c656 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SVD_Release()
822 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SwCPURst()
826 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_Sub_SwCPURst()
1042 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_Sub_SetRegCPU()
1045 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_Sub_SetRegCPU()
1048 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1052 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1057 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1062 HVD_SUB_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_Sub_SetRegCPU()
1063 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_Sub_SetRegCPU()
[all …]
H A DhalHVD.c669 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_SVD_Release()
835 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_SwCPURst()
839 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_SwCPURst()
1088 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_SetRegCPU()
1091 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_SetRegCPU()
1094 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1098 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1103 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_SetRegCPU()
1108 HVD_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_SetRegCPU()
1109 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_SetRegCPU()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DhalHVD_sub.c656 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SVD_Release()
822 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SwCPURst()
826 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_Sub_SwCPURst()
1042 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_Sub_SetRegCPU()
1045 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_Sub_SetRegCPU()
1048 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1052 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1057 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1062 HVD_SUB_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_Sub_SetRegCPU()
1063 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_Sub_SetRegCPU()
[all …]
H A DhalHVD.c669 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_SVD_Release()
835 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_SwCPURst()
839 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_SwCPURst()
1088 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_SetRegCPU()
1091 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_SetRegCPU()
1094 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1098 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1103 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_SetRegCPU()
1108 HVD_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_SetRegCPU()
1109 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_SetRegCPU()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DhalHVD_sub.c656 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SVD_Release()
822 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_Sub_SwCPURst()
826 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_Sub_SwCPURst()
1042 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_Sub_SetRegCPU()
1045 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_Sub_SetRegCPU()
1048 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1052 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1057 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_Sub_SetRegCPU()
1062 HVD_SUB_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_Sub_SetRegCPU()
1063 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_Sub_SetRegCPU()
[all …]
H A DhalHVD.c669 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST); in _HAL_SVD_Release()
835 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST); in _HAL_HVD_SwCPURst()
839 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) in _HAL_HVD_SwCPURst()
1088 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RE… in _HAL_HVD_SetRegCPU()
1091 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RES… in _HAL_HVD_SetRegCPU()
1094 …_HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1098 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE ); in _HAL_HVD_SetRegCPU()
1103 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE ); in _HAL_HVD_SetRegCPU()
1108 HVD_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET)); in _HAL_HVD_SetRegCPU()
1109 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in _HAL_HVD_SetRegCPU()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/hvd_ex/
H A DhalHVD_EX.c1561 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2282 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2284 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256); in HAL_HVD_EX_InitHW()
2340 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2355 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2360 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2364 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2389 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2401 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2405 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/hvd_ex/
H A DhalHVD_EX.c1561 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2282 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2284 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256); in HAL_HVD_EX_InitHW()
2340 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2355 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2360 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2364 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2389 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2401 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2405 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DhalHVD_EX.c2327 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
3479 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3481 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
3482 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256); in HAL_HVD_EX_InitHW()
3483 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256); in HAL_HVD_EX_InitHW()
3484 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256); in HAL_HVD_EX_InitHW()
3485 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128); in HAL_HVD_EX_InitHW()
3486 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128); in HAL_HVD_EX_InitHW()
3567 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
3586 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c2122 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
3456 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3458 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
3459 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256); in HAL_HVD_EX_InitHW()
3460 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256); in HAL_HVD_EX_InitHW()
3461 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256); in HAL_HVD_EX_InitHW()
3462 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128); in HAL_HVD_EX_InitHW()
3463 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128); in HAL_HVD_EX_InitHW()
3548 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
3567 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c2280 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
3531 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3533 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
3534 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256); in HAL_HVD_EX_InitHW()
3535 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256); in HAL_HVD_EX_InitHW()
3536 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256); in HAL_HVD_EX_InitHW()
3537 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128); in HAL_HVD_EX_InitHW()
3538 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128); in HAL_HVD_EX_InitHW()
3611 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
3630 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c2276 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
3572 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3574 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
3575 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256); in HAL_HVD_EX_InitHW()
3576 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256); in HAL_HVD_EX_InitHW()
3577 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256); in HAL_HVD_EX_InitHW()
3578 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128); in HAL_HVD_EX_InitHW()
3579 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128); in HAL_HVD_EX_InitHW()
3663 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
3682 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DhalHVD_EX.c1562 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2249 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2286 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2301 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2306 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2310 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2335 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2347 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2351 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
2354 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DhalHVD_EX.c1562 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2249 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2286 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2301 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2306 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2310 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2335 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2347 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2351 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
2354 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DhalHVD_EX.c1562 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2249 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2286 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2301 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2306 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2310 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2335 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2347 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2351 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
2354 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DhalHVD_EX.c1562 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2249 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2286 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2301 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2306 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2310 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2335 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2347 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2351 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
2354 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DhalHVD_EX.c1562 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2249 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2286 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2301 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2306 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2310 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2335 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2347 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2351 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
2354 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DhalHVD_EX.c1562 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2249 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2286 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2301 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2306 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2310 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2335 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2347 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2351 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
2354 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DhalHVD_EX.c1562 … HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET), in _HVD_EX_SetRegCPU()
2249 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
2286 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2301 _HVD_WriteWordMask(HVD_REG_RESET, 0, in HAL_HVD_EX_InitHW()
2306 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2310 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE); in HAL_HVD_EX_InitHW()
2335 … _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE); in HAL_HVD_EX_InitHW()
2347 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
2351 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128)); in HAL_HVD_EX_InitHW()
2354 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET)); in HAL_HVD_EX_InitHW()
[all …]

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