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Searched refs:FRONTENDEXT2_REG_BASE (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBS.c143 #define FRONTENDEXT2_REG_BASE 0x2300 macro
4602 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4650 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4651 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
4746 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_AGC_Info()
4794 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_AGC_Info()
4795 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBS.c145 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4175 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4223 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4224 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBS.c145 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4175 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4223 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4224 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBS.c145 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4020 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4068 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4069 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBS.c145 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4163 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4211 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4212 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBS.c145 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4163 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4211 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4212 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBS.c145 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4020 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4068 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4069 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBS.c145 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4020 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4068 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4069 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBS.c142 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
3959 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4007 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4008 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBS.c142 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4141 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4189 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4190 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBS.c142 #define FRONTENDEXT2_REG_BASE 0x2A00 macro
4162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref); in INTERN_DVBS_Show_AGC_Info()
4210 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp); in INTERN_DVBS_Show_AGC_Info()
4211 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03); in INTERN_DVBS_Show_AGC_Info()