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Searched refs:DMD_CLK_GEN (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBC.c1147 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBC_Adaptive_TS_CLK()
1149 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1152 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+1); in INTERN_DVBC_Adaptive_TS_CLK()
1158 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+1,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1161 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBC_Adaptive_TS_CLK()
1163 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1167 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBC_Adaptive_TS_CLK()
1169 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1182 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBC_Adaptive_TS_CLK()
H A DhalDMD_INTERN_DVBT.c1216 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBT_Adaptive_TS_CLK()
1218 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1221 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+1); in INTERN_DVBT_Adaptive_TS_CLK()
1223 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+1,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1226 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBT_Adaptive_TS_CLK()
1228 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1232 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBT_Adaptive_TS_CLK()
1234 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1247 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBT_Adaptive_TS_CLK()
H A DhalDMD_INTERN_common.h98 #define DMD_CLK_GEN 0x103300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBC.c1259 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBC_Adaptive_TS_CLK()
1261 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1264 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x01); in INTERN_DVBC_Adaptive_TS_CLK()
1270 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x01,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1273 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x00); in INTERN_DVBC_Adaptive_TS_CLK()
1275 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x00,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1278 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBC_Adaptive_TS_CLK()
1280 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
H A DhalDMD_INTERN_DVBT.c1399 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBT_Adaptive_TS_CLK()
1401 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1404 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x01); in INTERN_DVBT_Adaptive_TS_CLK()
1406 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x01,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1409 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBT_Adaptive_TS_CLK()
1411 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1414 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBT_Adaptive_TS_CLK()
1416 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
H A DhalDMD_INTERN_common.h98 #define DMD_CLK_GEN 0x103300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBC.c1259 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBC_Adaptive_TS_CLK()
1261 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1264 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x01); in INTERN_DVBC_Adaptive_TS_CLK()
1270 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x01,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1273 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x00); in INTERN_DVBC_Adaptive_TS_CLK()
1275 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x00,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1278 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBC_Adaptive_TS_CLK()
1280 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
H A DhalDMD_INTERN_DVBT.c1399 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBT_Adaptive_TS_CLK()
1401 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1404 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x01); in INTERN_DVBT_Adaptive_TS_CLK()
1406 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x01,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1409 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBT_Adaptive_TS_CLK()
1411 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1414 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBT_Adaptive_TS_CLK()
1416 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
H A DhalDMD_INTERN_common.h98 #define DMD_CLK_GEN 0x103300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBC.c1151 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBC_Adaptive_TS_CLK()
1153 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1156 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+1); in INTERN_DVBC_Adaptive_TS_CLK()
1162 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+1,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1165 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBC_Adaptive_TS_CLK()
1167 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1171 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBC_Adaptive_TS_CLK()
1173 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
1186 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBC_Adaptive_TS_CLK()
H A DhalDMD_INTERN_DVBT.c1224 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBT_Adaptive_TS_CLK()
1226 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1229 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+1); in INTERN_DVBT_Adaptive_TS_CLK()
1231 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+1,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1234 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBT_Adaptive_TS_CLK()
1236 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1240 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); in INTERN_DVBT_Adaptive_TS_CLK()
1242 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBT_Adaptive_TS_CLK()
1255 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN); in INTERN_DVBT_Adaptive_TS_CLK()
H A DhalDMD_INTERN_common.h98 #define DMD_CLK_GEN 0x103300 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBC.c2478 REG_CLK_bank_TS_div_num=DMD_CLK_GEN+0x00; in INTERN_DVBC_Adaptive_TS_CLK()
2483 REG_CLK_bank_TS_div_num=DMD_CLK_GEN+0x04*2; //checked in INTERN_DVBC_Adaptive_TS_CLK()
2509 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); //clock reset [bit 0] in INTERN_DVBC_Adaptive_TS_CLK()
2511 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
2514 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x01); //clock reset [bit 0] in INTERN_DVBC_Adaptive_TS_CLK()
2517 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x01,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
2525 TS_Clock_Temp=HAL_DMD_RIU_ReadByte(DMD_CLK_GEN+0x02); //release the reset [bit 0] in INTERN_DVBC_Adaptive_TS_CLK()
2527 HAL_DMD_RIU_WriteByte(DMD_CLK_GEN+0x02,TS_Clock_Temp); in INTERN_DVBC_Adaptive_TS_CLK()
H A DhalDMD_INTERN_common.h98 #define DMD_CLK_GEN 0x103300UL macro