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/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c271 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
296 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
300 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
301 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
307 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
311 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
312 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
318 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
322 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
323 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c278 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
303 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
307 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
308 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
314 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
318 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
319 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
325 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
329 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
330 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c278 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
303 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
307 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
308 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
314 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
318 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
319 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
325 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
329 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
330 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c202 MS_BOOL bCableDetect = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in _Hal_tmds_CheckInputIsMHL()
291 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
316 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
320 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
321 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
327 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
331 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
332 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
338 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
342 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c274 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
299 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
304 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
310 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
315 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
321 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
326 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c274 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
299 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
304 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
310 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
315 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
321 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
326 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c208 MS_BOOL bCableDetect = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in _Hal_tmds_CheckInputIsMHL()
297 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
322 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
326 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
327 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
333 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
338 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
344 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
348 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c208 MS_BOOL bCableDetect = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in _Hal_tmds_CheckInputIsMHL()
297 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
322 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
326 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
327 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
333 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
338 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
344 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
348 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c274 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
299 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
304 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
310 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
315 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
321 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
326 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(3), BIT(3)); in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c202 MS_BOOL bCableDetect = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in _Hal_tmds_CheckInputIsMHL()
335 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
357 if(usPacketInfoPortSelect1 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus1()
382 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
386 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
387 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
393 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
397 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
398 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
404 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c202 MS_BOOL bCableDetect = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in _Hal_tmds_CheckInputIsMHL()
335 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
357 if(usPacketInfoPortSelect1 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus1()
382 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
386 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
387 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
393 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(2)) // Get clock status in _Hal_tmds_GetClockValidFlag()
397 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
398 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(2), BIT(2)); in _Hal_tmds_GetClockValidFlag()
404 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(3)) // Get clock status in _Hal_tmds_GetClockValidFlag()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
163 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
177 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
182 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
186 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
191 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
192 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
163 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
177 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
182 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
186 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
191 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
192 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
163 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
177 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
182 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
186 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
191 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
192 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
163 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
177 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
182 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
186 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
191 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
192 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
163 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
177 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
182 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
186 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
191 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
192 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c151 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
152 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
154 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
163 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
166 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
168 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
171 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
175 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
180 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
181 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c151 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
152 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
154 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
163 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
166 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
168 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
171 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
175 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
180 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
181 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c145 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
146 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
148 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
157 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
160 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
162 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
165 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
169 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
174 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
175 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c145 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
146 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
148 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
157 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
160 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
162 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
165 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
169 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
174 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
175 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c167 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
168 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
170 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
179 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
182 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
184 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
187 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
191 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
196 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
197 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c167 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
168 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
170 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
179 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
182 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
184 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
187 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
191 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
196 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
197 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c175 return ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in _Hal_HDMI_GetMHLCableDetect()
257 …W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(15)|BIT(1), BIT(15)|BIT(1)); //[15]: Enable CPU write; [… in Hal_HDCP22_PortInit()
258 W2BYTEMSK(REG_HDCP_00_L + dwBKOffset, 0, BIT(1)); //[1]: disable SRAM read in Hal_HDCP22_PortInit()
261 W2BYTEMSK(REG_HDCP_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enable for DDC in Hal_HDCP22_PortInit()
262 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
265 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
268 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse generate in Hal_HDCP22_PortInit()
272 W2BYTEMSK(REG_HDCP22_P0_31_L + dwBKOffset22, BIT(15), BIT(15)); //reg_message_length_update in Hal_HDCP22_PortInit()
275 W2BYTEMSK(REG_HDCP22_P0_0E_L + dwBKOffset22, 0, BIT(0)); in Hal_HDCP22_PortInit()
293 if(R2BYTE(REG_HDCP22_P0_34_L) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c175 return ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in _Hal_HDMI_GetMHLCableDetect()
257 …W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(15)|BIT(1), BIT(15)|BIT(1)); //[15]: Enable CPU write; [… in Hal_HDCP22_PortInit()
258 W2BYTEMSK(REG_HDCP_00_L + dwBKOffset, 0, BIT(1)); //[1]: disable SRAM read in Hal_HDCP22_PortInit()
261 W2BYTEMSK(REG_HDCP_17_L + dwBKOffset, BIT(10), BIT(10)); //HDCP enable for DDC in Hal_HDCP22_PortInit()
262 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(15), BMASK(15:14)); //write enable in Hal_HDCP22_PortInit()
265 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(5), BIT(5)); //HDCP load address pulse in Hal_HDCP22_PortInit()
268 W2BYTEMSK(REG_HDCP_19_L + dwBKOffset, BIT(4), BIT(4)); //HDCP data write port pulse generate in Hal_HDCP22_PortInit()
272 W2BYTEMSK(REG_HDCP22_P0_31_L + dwBKOffset22, BIT(15), BIT(15)); //reg_message_length_update in Hal_HDCP22_PortInit()
275 W2BYTEMSK(REG_HDCP22_P0_0E_L + dwBKOffset22, 0, BIT(0)); in Hal_HDCP22_PortInit()
293 if(R2BYTE(REG_HDCP22_P0_34_L) & BIT(2)) //check write done in Hal_HDCP22_PollingWriteDone()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c279 if(usPacketInfoPortSelect0 &BIT(3)) in _Hal_tmds_GetPacketReceiveStatus0()
301 if(R2BYTE(REG_PM_SLEEP_04_L) &BIT(1)) // Get clock status in _Hal_tmds_GetClockValidFlag()
305 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
306 W2BYTEMSK(REG_PM_SLEEP_03_L, bCheckClockStable? 0: BIT(1), BIT(1)); in _Hal_tmds_GetClockValidFlag()
326 bStatusFlag = ((R2BYTE(REG_PM_SLEEP_3F_L) &BIT(14)) ?FALSE: TRUE); in _Hal_tmds_GetClockStableFlag()
399 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, bPowerOn? 0: (BIT(13)| BMASK(3:0)), BIT(13)| BMASK(3:0)); in _Hal_tmds_PowerDownControl()
414 W2BYTEMSK(REG_COMBO_PHY0_P0_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
415 …W2BYTEMSK(REG_COMBO_PHY0_P0_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
430 W2BYTEMSK(REG_PM_SLEEP_3A_L, BMASK(7:4)| BIT(1), BMASK(7:0)); in _Hal_tmds_ClockStatusInitial()
433 W2BYTEMSK(REG_PM_SLEEP_00_L, 0, BIT(1)); // Clock status mask in _Hal_tmds_ClockStatusInitial()
[all …]

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