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76 //******************************************************************************
77 //<MStar Software>
78 ///////////////////////////////////////////////////////////////////////////////////////////////////
79 ///
80 /// file mhal_mhl.c
81 /// @author MStar Semiconductor Inc.
82 /// @brief MHL driver Function
83 ///////////////////////////////////////////////////////////////////////////////////////////////////
84
85 #ifndef _MHAL_MHL_C_
86 #define _MHAL_MHL_C_
87
88 //-------------------------------------------------------------------------------------------------
89 // Include Files
90 //-------------------------------------------------------------------------------------------------
91 // Common Definition
92 #include "MsCommon.h"
93 #include "MsVersion.h"
94 #ifdef MSOS_TYPE_LINUX_KERNEL
95 #include <linux/string.h>
96 #else
97 #include <string.h>
98 #endif
99 #include "MsIRQ.h"
100 #include "MsOS.h"
101 #include "mhal_xc_chip_config.h"
102 #include "mhl_hwreg_utility2.h"
103 #include "hwreg_pm_sleep.h"
104 #include "hwreg_hdmi.h"
105 #include "hwreg_hdcp.h"
106 #include "hwregMHL.h"
107 #include "mdrv_mhl_st.h"
108 #include "halMHL.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Local Defines
112 //-------------------------------------------------------------------------------------------------
113 #define msg_mhl(x) x
114 #define MHL_DEBUG_SEND_MSC 0
115
116 #define DMHLInit 0
117
118 //-------------------------------------------------------------------------------------------------
119 // Local Structures
120 //-------------------------------------------------------------------------------------------------
121 typedef struct
122 {
123 MS_U32 addr;
124 MS_U16 mask;
125 MS_U16 databuf;
126 } msLoadTbl_S;
127
128 //-------------------------------------------------------------------------------------------------
129 // Global Variables
130 //-------------------------------------------------------------------------------------------------
131 MS_BOOL bMHLSignalStable = FALSE;
132 MS_BOOL bPortConfigChange = FALSE;
133 MS_BOOL bECbusEnableFlag = FALSE;
134 MS_U8 ucMHLSupportPort = E_MUX_NOT_SUPPORT_MHL;
135 MS_U8 ucIControlValue = MHL_ICONTROL_PD_24BIT_MODE0;
136 MS_U8 ucImpedanceValue = MHL_IMPEDANCE_VALUE;
137 MS_U8 ucChipIDValue = MHL_CHIP_ID_MONET;
138 MS_U8 ucECbusTrainState = MHL_ECBUS_STATE_DISABLE;
139 MS_U8 ucECbusTrainFailCount = 0;
140 MS_U8 ucMHL3LinkRate = MHL_AV_LINK_NONE;
141
142 //-------------------------------------------------------------------------------------------------
143 // MHL initial table
144 //-------------------------------------------------------------------------------------------------
145 static msLoadTbl_S tMHL_INITIAL_TABLE[] =
146 {
147 // Set accepted discover pulse high pulse width to ignore USB pulse
148 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
149 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
150 // CTS 4.3.7.1
151 {REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitration
152 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
153
154 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
155
156 // For CTS 6.3.10.7
157 {REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
158 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
159
160 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
161
162 #if(MHL_CBUS_OPERATION_MODE >= MHL_CBUS_HW_ISR_MODE)
163 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_devcap request
164 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
165 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
166 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
167 #else
168 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
169 {REG_MHL_CBUS_6D, BMASK(11:0), 0}, // Enable MHL HW mode
170 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), 0},
171 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
172 #endif
173
174 #if(MHL_CBUS_OPERATION_MODE == MHL_CBUS_HW_REPLY_MODE)
175 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
176 #endif
177
178 #if DMHL_INT_ENABLE
179 // Mask unused interrupt events
180 {REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_state_chg_int mask
181 {REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confirm_int mask, [5]: wakeup_pul_confirm_int mask, [1]: cbus_stuck_to_low_int mask.
182 {REG_PM_MHL_CBUS_30, BIT(1), BIT(1)}, // [1]: cbus conflict_int mask
183 {REG_PM_MHL_CBUS_38, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mask, [9]: unused mask, [5]: unused mask, [1]: unused mask.
184 {REG_MHL_CBUS_14, BIT(13), BIT(13)}, // [13]: int mask for monitor_sram_full
185 {REG_MHL_CBUS_18, BIT(13), BIT(13)}, // [13]: send rcv_pkt_ddc_sw_overwrite_err_in mask
186 {REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1]: send ddc error interrupt mask
187 {REG_MHL_CBUS_1B, BIT(1), BIT(1)}, // [1]: receive ddc packet valid mask
188 {REG_MHL_CBUS_1F, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: ddc access edid timeout int mask, [1]: client_wrt_ddc_ram interrupt mask
189 {REG_MHL_CBUS_21, BIT(5), BIT(5)}, // [5]: ddc error interrupt mask
190 {REG_MHL_CBUS_22, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: ddc access hdcp timeout int mask, [5]: receive nack pkt int_mask, [1]: receive abort pkt int mask
191 {REG_MHL_CBUS_23, BIT(13), BIT(13)}, // [13]: send rcv_pkt_msc_sw_overwrite_err_in mask
192 {REG_MHL_CBUS_24, BIT(1), BIT(1)}, // [1]: send error interrupt mask
193 {REG_MHL_CBUS_25, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: response_pkt_msc_hw_int mask, [5]: snd_pkt_msc_hw_int mask, [1]: msc sw send complete interrupt mask
194 {REG_MHL_CBUS_63, BIT(9), BIT(9)}, // [9]: dytycycle_bad_int mask
195 {REG_MHL_CBUS_65, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: rcv_parity_err_int mask, [5]: rcv_data_err_int mask, [1]: rcv_sync_err_int mask
196 {REG_MHL_CBUS_78, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mask, [9]: unused mask, [5]: unused mask, [1]: unused mask.
197 #endif
198 };
199
200 //-------------------------------------------------------------------------------------------------
201 // MHL power on table
202 //-------------------------------------------------------------------------------------------------
203 static msLoadTbl_S tMHL_POWER_ON_TABLE[] =
204 {
205 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
206 };
207
208 //-------------------------------------------------------------------------------------------------
209 // MHL power down table
210 //-------------------------------------------------------------------------------------------------
211 static msLoadTbl_S tMHL_POWER_DOWN_TABLE[] =
212 {
213 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
214 };
215
216 //-------------------------------------------------------------------------------------------------
217 // MHL power saving table
218 //-------------------------------------------------------------------------------------------------
219 static msLoadTbl_S tMHL_POWER_SAVING_TABLE[] =
220 {
221 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
222 };
223
224 //-------------------------------------------------------------------------------------------------
225 // Local Functions
226 //-------------------------------------------------------------------------------------------------
227
228 //**************************************************************************
229 // [Function Name]:
230 // _mhal_mhl_IsCbusBusy()
231 // [Description]
232 //
233 // [Arguments]:
234 //
235 // [Return]:
236 //
237 //**************************************************************************
_mhal_mhl_IsCbusBusy(void)238 MS_BOOL _mhal_mhl_IsCbusBusy(void)
239 {
240 MS_BOOL bBusyFlag = FALSE;
241
242 if(!bECbusEnableFlag)
243 {
244 bBusyFlag = ((R2BYTE(REG_MHL_CBUS_5D) & 0x00F0) != 0 ? TRUE : FALSE);
245 }
246 return bBusyFlag;
247 }
248
249 //**************************************************************************
250 // [Function Name]:
251 // _mhal_mhl_DviAutoEQSwitch()
252 // [Description]
253 //
254 // [Arguments]:
255 //
256 // [Return]:
257 //
258 //**************************************************************************
_mhal_mhl_DviAutoEQSwitch(MS_U8 ucCbusSelect,MS_BOOL bFlag)259 void _mhal_mhl_DviAutoEQSwitch(MS_U8 ucCbusSelect, MS_BOOL bFlag)
260 {
261 static MS_BOOL bAutoEQFlag = FALSE;
262
263 switch(ucCbusSelect)
264 {
265 #if(MHL_FUNCTION_SUPPORT_PORTA)
266 case MHL_CBUS_SELECT_PORTA:
267 if(GET_MHL_PATH_SUPPORT_PORTA())
268 {
269 if(!bAutoEQFlag)
270 {
271 //if((R2BYTE(REG_DVI_DTOP_DUAL_P0_2F_L) &BIT(0)) == BIT(0))
272 {
273 bAutoEQFlag = TRUE;
274 }
275 }
276
277 if(bAutoEQFlag)
278 {
279 if(bFlag)
280 {
281 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_00_L, BIT(4), BIT(4)); // enable EQ new mode
282 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
283 }
284 else
285 {
286 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_00_L, 0, BIT(4)); // disable EQ new mode
287 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_2F_L, 0, BIT(0)); // disable autoEQ controller
288 }
289 }
290 }
291
292 break;
293 #endif
294
295 #if(MHL_FUNCTION_SUPPORT_PORTB)
296 case MHL_CBUS_SELECT_PORTB:
297 if(GET_MHL_PATH_SUPPORT_PORTB())
298 {
299 if(!bAutoEQFlag)
300 {
301 //if((R2BYTE(REG_DVI_DTOP_DUAL_P1_2F_L) &BIT(0)) == BIT(0))
302 {
303 bAutoEQFlag = TRUE;
304 }
305 }
306
307 if(bAutoEQFlag)
308 {
309 if(bFlag)
310 {
311 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_00_L, BIT(4), BIT(4)); // enable EQ new mode
312 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
313 }
314 else
315 {
316 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_00_L, 0, BIT(4)); // disable EQ new mode
317 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_2F_L, 0, BIT(0)); // disable autoEQ controller
318 }
319 }
320 }
321
322 break;
323 #endif
324
325 #if(MHL_FUNCTION_SUPPORT_PORTC)
326 case MHL_CBUS_SELECT_PORTC:
327 if(GET_MHL_PATH_SUPPORT_PORTC())
328 {
329 if(!bAutoEQFlag)
330 {
331 //if((R2BYTE(REG_DVI_DTOP_DUAL_P2_2F_L) &BIT(0)) == BIT(0))
332 {
333 bAutoEQFlag = TRUE;
334 }
335 }
336
337 if(bAutoEQFlag)
338 {
339 if(bFlag)
340 {
341 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_00_L, BIT(4), BIT(4)); // enable EQ new mode
342 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
343 }
344 else
345 {
346 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_00_L, 0, BIT(4)); // disable EQ new mode
347 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_2F_L, 0, BIT(0)); // disable autoEQ controller
348 }
349 }
350 }
351
352 break;
353 #endif
354
355 #if(MHL_FUNCTION_SUPPORT_PORTD)
356 case MHL_CBUS_SELECT_PORTD:
357 if(GET_MHL_PATH_SUPPORT_PORTD())
358 {
359 if(!bAutoEQFlag)
360 {
361 //if((R2BYTE(REG_DVI_DTOP_DUAL_P3_2F_L) &BIT(0)) == BIT(0))
362 {
363 bAutoEQFlag = TRUE;
364 }
365 }
366
367 if(bAutoEQFlag)
368 {
369 if(bFlag)
370 {
371 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_00_L, BIT(4), BIT(4)); // enable EQ new mode
372 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
373 }
374 else
375 {
376 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_00_L, 0, BIT(4)); // disable EQ new mode
377 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_2F_L, 0, BIT(0)); // disable autoEQ controller
378 }
379 }
380 }
381
382 break;
383 #endif
384
385 default:
386
387 break;
388 };
389 }
390
391 //**************************************************************************
392 // [Function Name]:
393 // _mhal_mhl_HdmiBypassModeSetting()
394 // [Description]
395 // MHL HDMI bypass setting
396 // [Arguments]:
397 //
398 // [Return]:
399 //
400 //**************************************************************************
_mhal_mhl_HdmiBypassModeSetting(MS_U8 ucCbusSelect)401 void _mhal_mhl_HdmiBypassModeSetting(MS_U8 ucCbusSelect)
402 {
403 switch(ucCbusSelect)
404 {
405 #if(MHL_FUNCTION_SUPPORT_PORTA)
406 case MHL_CBUS_SELECT_PORTA:
407 if(GET_MHL_PATH_SUPPORT_PORTA())
408 {
409 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
410 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ
411 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0));
412 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble
413 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write
414 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
415
416 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
417 {
418 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, 0, BIT(8));
419 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12));
420 }
421 }
422
423 break;
424 #endif
425
426 #if(MHL_FUNCTION_SUPPORT_PORTB)
427 case MHL_CBUS_SELECT_PORTB:
428 if(GET_MHL_PATH_SUPPORT_PORTB())
429 {
430 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
431 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ
432 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0));
433 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble
434 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, 0, BIT(10)); // I-control PD overwrite write
435 W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
436
437 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
438 {
439 W2BYTEMSK(REG_COMBO_PHY0_P1_59_L, 0, BIT(8));
440 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12));
441 }
442 }
443
444 break;
445 #endif
446
447 #if(MHL_FUNCTION_SUPPORT_PORTC)
448 case MHL_CBUS_SELECT_PORTC:
449 if(GET_MHL_PATH_SUPPORT_PORTC())
450 {
451 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
452 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ
453 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0));
454 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble
455 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, 0, BIT(10)); // I-control PD overwrite write
456 W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
457
458 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
459 {
460 W2BYTEMSK(REG_COMBO_PHY0_P2_59_L, 0, BIT(8));
461 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12));
462 }
463 }
464
465 break;
466 #endif
467
468 #if(MHL_FUNCTION_SUPPORT_PORTD)
469 case MHL_CBUS_SELECT_PORTD:
470 if(GET_MHL_PATH_SUPPORT_PORTD())
471 {
472 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
473 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ
474 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0));
475 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble
476 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, 0, BIT(10)); // I-control PD overwrite write
477 W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
478
479 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
480 {
481 W2BYTEMSK(REG_COMBO_PHY0_P3_59_L, 0, BIT(8));
482 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (MHL_IMPEDANCE_VALUE << 12), BMASK(15:12));
483 }
484 }
485
486 break;
487 #endif
488
489 default:
490
491 break;
492 };
493
494 _mhal_mhl_DviAutoEQSwitch(ucCbusSelect, TRUE);
495 }
496
497 //**************************************************************************
498 // [Function Name]:
499 // _mhal_mhl_Mhl24bitsModeSetting()
500 // [Description]
501 // MHL 24 bits mode setting
502 // [Arguments]:
503 //
504 // [Return]:
505 //
506 //**************************************************************************
_mhal_mhl_Mhl24bitsModeSetting(MS_U8 ucCbusSelect)507 void _mhal_mhl_Mhl24bitsModeSetting(MS_U8 ucCbusSelect)
508 {
509 switch(ucCbusSelect)
510 {
511 #if(MHL_FUNCTION_SUPPORT_PORTA)
512 case MHL_CBUS_SELECT_PORTA:
513 if(GET_MHL_PATH_SUPPORT_PORTA())
514 {
515 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
516 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
517 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0));
518 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble
519 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write
520 W2BYTEMSK(REG_COMBO_PHY0_P0_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD
521 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
522
523 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
524 {
525 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, BIT(8), BIT(8));
526 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (ucImpedanceValue << 12), BMASK(15:12));
527 }
528 }
529
530 break;
531 #endif
532
533 #if(MHL_FUNCTION_SUPPORT_PORTB)
534 case MHL_CBUS_SELECT_PORTB:
535 if(GET_MHL_PATH_SUPPORT_PORTB())
536 {
537 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
538 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
539 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0));
540 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble
541 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write
542 W2BYTEMSK(REG_COMBO_PHY0_P1_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD
543 W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
544
545 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
546 {
547 W2BYTEMSK(REG_COMBO_PHY0_P1_59_L, BIT(8), BIT(8));
548 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (ucImpedanceValue << 12), BMASK(15:12));
549 }
550 }
551
552 break;
553 #endif
554
555 #if(MHL_FUNCTION_SUPPORT_PORTC)
556 case MHL_CBUS_SELECT_PORTC:
557 if(GET_MHL_PATH_SUPPORT_PORTC())
558 {
559 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
560 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
561 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0));
562 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble
563 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write
564 W2BYTEMSK(REG_COMBO_PHY0_P2_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD
565 W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
566
567 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
568 {
569 W2BYTEMSK(REG_COMBO_PHY0_P2_59_L, BIT(8), BIT(8));
570 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (ucImpedanceValue << 12), BMASK(15:12));
571 }
572 }
573
574 break;
575 #endif
576
577 #if(MHL_FUNCTION_SUPPORT_PORTD)
578 case MHL_CBUS_SELECT_PORTD:
579 if(GET_MHL_PATH_SUPPORT_PORTD())
580 {
581 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
582 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
583 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0));
584 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble
585 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write
586 W2BYTEMSK(REG_COMBO_PHY0_P3_6C_L, (MHL_ICONTROL_PD_VALUE << 9), BMASK(13:9)); // I-control PD
587 W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
588
589 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
590 {
591 W2BYTEMSK(REG_COMBO_PHY0_P3_59_L, BIT(8), BIT(8));
592 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (ucImpedanceValue << 12), BMASK(15:12));
593 }
594 }
595
596 break;
597 #endif
598
599 default:
600
601 break;
602 };
603
604 _mhal_mhl_DviAutoEQSwitch(ucCbusSelect, FALSE);
605 }
606
607 //**************************************************************************
608 // [Function Name]:
609 // _mhal_mhl_MhlPackedPixelModeSetting()
610 // [Description]
611 // MHL packed pixel mode setting
612 // [Arguments]:
613 //
614 // [Return]:
615 //
616 //**************************************************************************
_mhal_mhl_MhlPackedPixelModeSetting(MS_U8 ucCbusSelect)617 void _mhal_mhl_MhlPackedPixelModeSetting(MS_U8 ucCbusSelect)
618 {
619 switch(ucCbusSelect)
620 {
621 #if(MHL_FUNCTION_SUPPORT_PORTA)
622 case MHL_CBUS_SELECT_PORTA:
623 if(GET_MHL_PATH_SUPPORT_PORTA())
624 {
625 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode
626 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
627 }
628
629 break;
630 #endif
631
632 #if(MHL_FUNCTION_SUPPORT_PORTB)
633 case MHL_CBUS_SELECT_PORTB:
634 if(GET_MHL_PATH_SUPPORT_PORTB())
635 {
636 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode
637 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
638 }
639
640 break;
641 #endif
642
643 #if(MHL_FUNCTION_SUPPORT_PORTC)
644 case MHL_CBUS_SELECT_PORTC:
645 if(GET_MHL_PATH_SUPPORT_PORTC())
646 {
647 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode
648 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
649 }
650
651 break;
652 #endif
653
654 #if(MHL_FUNCTION_SUPPORT_PORTD)
655 case MHL_CBUS_SELECT_PORTD:
656 if(GET_MHL_PATH_SUPPORT_PORTD())
657 {
658 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode
659 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
660 }
661
662 break;
663 #endif
664
665 default:
666
667 break;
668 };
669 }
670
671 //**************************************************************************
672 // [Function Name]:
673 // _mhal_mhl_RxRtermControl()
674 // [Description]
675 // MHL TMDS termination resistor control
676 // [Arguments]:
677 //
678 // [Return]:
679 //
680 //**************************************************************************
_mhal_mhl_RxRtermControl(MS_U8 ucCbusSelect,RXRtermControl_T rctrl)681 void _mhal_mhl_RxRtermControl(MS_U8 ucCbusSelect, RXRtermControl_T rctrl)
682 {
683 switch(ucCbusSelect)
684 {
685 #if(MHL_FUNCTION_SUPPORT_PORTA)
686 case MHL_CBUS_SELECT_PORTA:
687 if(GET_MHL_PATH_SUPPORT_PORTA())
688 {
689 if (rctrl == RX_HDMI_RTERM)
690 {
691 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term
692 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term
693 }
694 else if (rctrl == RX_MHL_RTERM)
695 {
696 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term
697 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term
698 }
699 else if (rctrl == RX_RTERM_OFF)
700 {
701 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term
702 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term
703 }
704 }
705
706 break;
707 #endif
708
709 #if(MHL_FUNCTION_SUPPORT_PORTB)
710 case MHL_CBUS_SELECT_PORTB:
711 if(GET_MHL_PATH_SUPPORT_PORTB())
712 {
713 if (rctrl == RX_HDMI_RTERM)
714 {
715 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term
716 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term
717 }
718 else if (rctrl == RX_MHL_RTERM)
719 {
720 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term
721 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term
722 }
723 else if (rctrl == RX_RTERM_OFF)
724 {
725 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(7:5), BMASK(7:5));// data R-term
726 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(4), BIT(4));// clock R-term
727 }
728 }
729
730 break;
731 #endif
732
733 #if(MHL_FUNCTION_SUPPORT_PORTC)
734 case MHL_CBUS_SELECT_PORTC:
735 if(GET_MHL_PATH_SUPPORT_PORTC())
736 {
737 if (rctrl == RX_HDMI_RTERM)
738 {
739 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(11:9));// data R-term
740 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term
741 }
742 else if (rctrl == RX_MHL_RTERM)
743 {
744 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term
745 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term
746 }
747 else if (rctrl == RX_RTERM_OFF)
748 {
749 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(11:9), BMASK(11:9));// data R-term
750 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(8), BIT(8));// clock R-term
751 }
752 }
753
754 break;
755 #endif
756
757 #if(MHL_FUNCTION_SUPPORT_PORTD)
758 case MHL_CBUS_SELECT_PORTD:
759 if(GET_MHL_PATH_SUPPORT_PORTD())
760 {
761 if (rctrl == RX_HDMI_RTERM)
762 {
763 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(15:13));// data R-term
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term
765 }
766 else if (rctrl == RX_MHL_RTERM)
767 {
768 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term
769 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term
770 }
771 else if (rctrl == RX_RTERM_OFF)
772 {
773 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(15:13), BMASK(15:13));// data R-term
774 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(12), BIT(12));// clock R-term
775 }
776 }
777
778 break;
779 #endif
780
781 default:
782
783 break;
784 };
785 }
786
787 //**************************************************************************
788 // [Function Name]:
789 // _mhal_mhl_CbusForceToStandby()
790 // [Description]
791 //
792 // [Arguments]:
793 //
794 // [Return]:
795 //
796 //**************************************************************************
_mhal_mhl_CbusForceToStandby(void)797 void _mhal_mhl_CbusForceToStandby(void)
798 {
799 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO
800 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode
801 }
802
803 //**************************************************************************
804 // [Function Name]:
805 // _mhal_mhl_MHLForceToAttach()
806 // [Description]:
807 //
808 // [Arguments]:
809 //
810 // [Return]:
811 //
812 //**************************************************************************
_mhal_mhl_MHLForceToAttach(void)813 void _mhal_mhl_MHLForceToAttach(void)
814 {
815 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14));
816 }
817
818 #if(DMHL_LG_PRADA_PATCH)
819 //**************************************************************************
820 // [Function Name]:
821 // _mhal_mhl_AdjustCommonModeResistor()
822 // [Description]:
823 //
824 // [Arguments]:
825 //
826 // [Return]:
827 //
828 //**************************************************************************
_mhal_mhl_AdjustCommonModeResistor(MS_U8 ucCbusSelect,MS_BOOL bflag)829 void _mhal_mhl_AdjustCommonModeResistor(MS_U8 ucCbusSelect, MS_BOOL bflag)
830 {
831 switch(ucCbusSelect)
832 {
833 #if(MHL_FUNCTION_SUPPORT_PORTA)
834 case MHL_CBUS_SELECT_PORTA:
835 if(GET_MHL_PATH_SUPPORT_PORTA())
836 {
837 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable
838 }
839
840 break;
841 #endif
842
843 #if(MHL_FUNCTION_SUPPORT_PORTB)
844 case MHL_CBUS_SELECT_PORTB:
845 if(GET_MHL_PATH_SUPPORT_PORTB())
846 {
847 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable
848 }
849
850 break;
851 #endif
852
853 #if(MHL_FUNCTION_SUPPORT_PORTC)
854 case MHL_CBUS_SELECT_PORTC:
855 if(GET_MHL_PATH_SUPPORT_PORTC())
856 {
857 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable
858 }
859
860 break;
861 #endif
862
863 #if(MHL_FUNCTION_SUPPORT_PORTD)
864 case MHL_CBUS_SELECT_PORTD:
865 if(GET_MHL_PATH_SUPPORT_PORTD())
866 {
867 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable
868 }
869
870 break;
871 #endif
872
873 default:
874
875 break;
876 };
877 }
878
879 #endif
880
881 //**************************************************************************
882 // [Function Name]:
883 // _mhal_mhl_ClockBigChangeFlag()
884 // [Description]:
885 //
886 // [Arguments]:
887 //
888 // [Return]:
889 //
890 //**************************************************************************
_mhal_mhl_ClockBigChangeFlag(MS_U8 ucCbusSelect)891 MS_BOOL _mhal_mhl_ClockBigChangeFlag(MS_U8 ucCbusSelect)
892 {
893 MS_BOOL bindex = FALSE;
894
895 switch(ucCbusSelect)
896 {
897 #if(MHL_FUNCTION_SUPPORT_PORTA)
898 case MHL_CBUS_SELECT_PORTA:
899 if(GET_MHL_PATH_SUPPORT_PORTA())
900 {
901 //bindex = ((R2BYTE(REG_DVI_ATOP_70_L) &BIT(0)) ?TRUE: FALSE);
902
903 if(bindex)
904 {
905 //W2BYTEMSK(REG_DVI_ATOP_71_L, BIT(8), BIT(8));
906 //W2BYTEMSK(REG_DVI_ATOP_71_L, 0, BIT(8));
907 }
908 }
909
910 break;
911 #endif
912
913 #if(MHL_FUNCTION_SUPPORT_PORTB)
914 case MHL_CBUS_SELECT_PORTB:
915 if(GET_MHL_PATH_SUPPORT_PORTB())
916 {
917 //bindex = ((R2BYTE(REG_DVI_ATOP1_70_L) &BIT(0)) ?TRUE: FALSE);
918
919 if(bindex)
920 {
921 //W2BYTEMSK(REG_DVI_ATOP1_71_L, BIT(8), BIT(8));
922 //W2BYTEMSK(REG_DVI_ATOP1_71_L, 0, BIT(8));
923 }
924 }
925
926 break;
927 #endif
928
929 #if(MHL_FUNCTION_SUPPORT_PORTC)
930 case MHL_CBUS_SELECT_PORTC:
931 if(GET_MHL_PATH_SUPPORT_PORTC())
932 {
933 //bindex = ((R2BYTE(REG_DVI_ATOP3_70_L) &BIT(0)) ?TRUE: FALSE);
934
935 if(bindex)
936 {
937 //W2BYTEMSK(REG_DVI_ATOP3_71_L, BIT(8), BIT(8));
938 //W2BYTEMSK(REG_DVI_ATOP3_71_L, 0, BIT(8));
939 }
940 }
941
942 break;
943 #endif
944
945 #if(MHL_FUNCTION_SUPPORT_PORTD)
946 case MHL_CBUS_SELECT_PORTD:
947 if(GET_MHL_PATH_SUPPORT_PORTD())
948 {
949 //bindex = ((R2BYTE(REG_DVI_ATOP2_70_L) &BIT(0)) ?TRUE: FALSE);
950
951 if(bindex)
952 {
953 //W2BYTEMSK(REG_DVI_ATOP2_71_L, BIT(8), BIT(8));
954 //W2BYTEMSK(REG_DVI_ATOP2_71_L, 0, BIT(8));
955 }
956 }
957
958 break;
959 #endif
960
961 default:
962
963 break;
964 };
965
966 return bindex;
967 }
968
969 //**************************************************************************
970 // [Function Name]:
971 // _mhal_mhl_CheckClockStatus()
972 // [Description]:
973 //
974 // [Arguments]:
975 //
976 // [Return]:
977 //
978 //**************************************************************************
_mhal_mhl_CheckClockStatus(MS_U8 ucCbusSelect)979 MS_U8 _mhal_mhl_CheckClockStatus(MS_U8 ucCbusSelect)
980 {
981 MS_BOOL bStable = FALSE;
982 MS_U16 usClkCount = 0;
983
984 switch(ucCbusSelect)
985 {
986 #if(MHL_FUNCTION_SUPPORT_PORTA)
987 case MHL_CBUS_SELECT_PORTA:
988 if(GET_MHL_PATH_SUPPORT_PORTA())
989 {
990 usClkCount = R2BYTE(REG_COMBO_PHY0_P0_3C_L) & 0x0FFF;
991
992 if((R2BYTE(REG_COMBO_PHY0_P0_41_L) &BIT(9)) == BIT(9))
993 {
994 bStable = TRUE;
995
996 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
997 {
998 bStable = FALSE;
999 }
1000 }
1001 }
1002
1003 break;
1004 #endif
1005
1006 #if(MHL_FUNCTION_SUPPORT_PORTB)
1007 case MHL_CBUS_SELECT_PORTB:
1008 if(GET_MHL_PATH_SUPPORT_PORTB())
1009 {
1010 usClkCount = R2BYTE(REG_COMBO_PHY0_P1_3C_L) & 0x0FFF;
1011
1012 if((R2BYTE(REG_COMBO_PHY0_P1_41_L) &BIT(9)) == BIT(9))
1013 {
1014 bStable = TRUE;
1015
1016 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1017 {
1018 bStable = FALSE;
1019 }
1020 }
1021 }
1022
1023 break;
1024 #endif
1025
1026 #if(MHL_FUNCTION_SUPPORT_PORTC)
1027 case MHL_CBUS_SELECT_PORTC:
1028 if(GET_MHL_PATH_SUPPORT_PORTC())
1029 {
1030 usClkCount = R2BYTE(REG_COMBO_PHY0_P2_3C_L) & 0x0FFF;
1031
1032 if((R2BYTE(REG_COMBO_PHY0_P2_41_L) &BIT(9)) == BIT(9))
1033 {
1034 bStable = TRUE;
1035
1036 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1037 {
1038 bStable = FALSE;
1039 }
1040 }
1041 }
1042
1043 break;
1044 #endif
1045
1046 #if(MHL_FUNCTION_SUPPORT_PORTD)
1047 case MHL_CBUS_SELECT_PORTD:
1048 if(GET_MHL_PATH_SUPPORT_PORTD())
1049 {
1050 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF;
1051
1052 if((R2BYTE(REG_COMBO_PHY0_P3_41_L) &BIT(9)) == BIT(9))
1053 {
1054 bStable = TRUE;
1055
1056 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1057 {
1058 bStable = FALSE;
1059 }
1060 }
1061 }
1062
1063 break;
1064 #endif
1065
1066 default:
1067
1068 break;
1069 };
1070
1071 return bStable;
1072 }
1073
1074 //**************************************************************************
1075 // [Function Name]:
1076 // _mhal_mhl_RtermHWControl()
1077 // [Description]
1078 //
1079 // [Arguments]:
1080 //
1081 // [Return]:
1082 //
1083 //**************************************************************************
_mhal_mhl_RtermHWControl(MS_U8 ucCbusSelect,MS_BOOL bFlag)1084 void _mhal_mhl_RtermHWControl(MS_U8 ucCbusSelect, MS_BOOL bFlag)
1085 {
1086 switch(ucCbusSelect)
1087 {
1088 #if(MHL_FUNCTION_SUPPORT_PORTA)
1089 case MHL_CBUS_SELECT_PORTA:
1090 if(GET_MHL_PATH_SUPPORT_PORTA())
1091 {
1092 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8));
1093 }
1094
1095 break;
1096 #endif
1097
1098 #if(MHL_FUNCTION_SUPPORT_PORTB)
1099 case MHL_CBUS_SELECT_PORTB:
1100 if(GET_MHL_PATH_SUPPORT_PORTB())
1101 {
1102 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9));
1103 }
1104
1105 break;
1106 #endif
1107
1108 #if(MHL_FUNCTION_SUPPORT_PORTC)
1109 case MHL_CBUS_SELECT_PORTC:
1110 if(GET_MHL_PATH_SUPPORT_PORTC())
1111 {
1112 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10));
1113 }
1114
1115 break;
1116 #endif
1117
1118 #if(MHL_FUNCTION_SUPPORT_PORTD)
1119 case MHL_CBUS_SELECT_PORTD:
1120 if(GET_MHL_PATH_SUPPORT_PORTD())
1121 {
1122 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11));
1123 }
1124
1125 break;
1126 #endif
1127
1128 default:
1129
1130 break;
1131 };
1132 }
1133
1134 //**************************************************************************
1135 // [Function Name]:
1136 // _mhal_mhl_ChangeScalerMainMux()
1137 // [Description]
1138 //
1139 // [Arguments]:
1140 //
1141 // [Return]:
1142 //
1143 //**************************************************************************
_mhal_mhl_ChangeScalerMainMux(MS_BOOL bFlag)1144 void _mhal_mhl_ChangeScalerMainMux(MS_BOOL bFlag)
1145 {
1146 MS_U8 ucScalerMainMux = (R2BYTE(0x102E02) &BMASK(7:4)) >> 4;
1147
1148 if(bFlag)
1149 {
1150 if(ucScalerMainMux == MHL_SCALER_MUX_SELECT_DVI)
1151 {
1152 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4));
1153 }
1154 }
1155 else
1156 {
1157 if(ucScalerMainMux == MHL_SCALER_MUX_SELECT_MHL)
1158 {
1159 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4));
1160 }
1161 }
1162 }
1163
1164 //**************************************************************************
1165 // [Function Name]:
1166 // _mhal_mhl_AudioPathSelect()
1167 // [Description]
1168 //
1169 // [Arguments]:
1170 //
1171 // [Return]:
1172 //
1173 //**************************************************************************
_mhal_mhl_AudioPathSelect(MS_BOOL bMHLPath)1174 void _mhal_mhl_AudioPathSelect(MS_BOOL bMHLPath)
1175 {
1176 //W2BYTEMSK(REG_HDMI2_08_L, bMHLPath ?BIT(0) :0, BIT(0)); // [0]: audio source selection, 0: HDMI / 1: MHL
1177 }
1178
1179 //**************************************************************************
1180 // [Function Name]:
1181 // _mhal_mhl_CbusAndClockSelect()
1182 // [Description]
1183 //
1184 // [Arguments]:
1185 //
1186 // [Return]:
1187 //
1188 //**************************************************************************
_mhal_mhl_CbusAndClockSelect(void)1189 void _mhal_mhl_CbusAndClockSelect(void)
1190 {
1191 MS_U8 ucClockSelect = MHL_DVI_PORT_A;
1192
1193 if(GET_MHL_PATH_SUPPORT_PORTA())
1194 {
1195 ucClockSelect = MHL_DVI_PORT_A;
1196 }
1197 else if(GET_MHL_PATH_SUPPORT_PORTB())
1198 {
1199 ucClockSelect = MHL_DVI_PORT_B;
1200 }
1201 else if(GET_MHL_PATH_SUPPORT_PORTC())
1202 {
1203 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(6)| BIT(8)| BIT(0)); // [0]: reg_hplugc_mhl_en
1204 ucClockSelect = MHL_DVI_PORT_C;
1205 }
1206 else if(GET_MHL_PATH_SUPPORT_PORTD())
1207 {
1208 ucClockSelect = MHL_DVI_PORT_D;
1209 }
1210
1211 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select
1212 }
1213
1214 //**************************************************************************
1215 // [Function Name]:
1216 // _mhal_mhl_ForcePullDown100K()
1217 // [Description]
1218 //
1219 // [Arguments]:
1220 //
1221 // [Return]:
1222 //
1223 //**************************************************************************
_mhal_mhl_ForcePullDown100K(MS_BOOL bEnable)1224 void _mhal_mhl_ForcePullDown100K(MS_BOOL bEnable)
1225 {
1226 W2BYTEMSK(REG_PM_MHL_CBUS_20, bEnable? BIT(7): 0, BIT(7));
1227 }
1228
1229 //**************************************************************************
1230 // [Function Name]:
1231 // _mhal_mhl_GetEMSCOneByteCRC()
1232 // [Description]
1233 //
1234 // [Arguments]:
1235 //
1236 // [Return]:
1237 //
1238 //**************************************************************************
_mhal_mhl_GetEMSCOneByteCRC(MS_U8 ucOpCode)1239 MS_U8 _mhal_mhl_GetEMSCOneByteCRC(MS_U8 ucOpCode)
1240 {
1241 MS_U8 ucAValue = 0;
1242 MS_U8 ucBValue = 0;
1243 MS_U8 ucCommand = BIT(7) |BIT(6) |((ucOpCode &BMASK(2:0)) << 2);
1244
1245 ucAValue = GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BIT(3)) +2;
1246 ucBValue = GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(4)) +GET_BIT(ucCommand &BIT(2)) +2;
1247
1248 if(ucAValue &BIT(0))
1249 {
1250 ucCommand |= BIT(1);
1251 }
1252
1253 if(ucBValue &BIT(0))
1254 {
1255 ucCommand |= BIT(0);
1256 }
1257
1258 return ucCommand;
1259 }
1260
1261 //**************************************************************************
1262 // [Function Name]:
1263 // _mhal_mhl_GetEMSCTwoByteCRC()
1264 // [Description]
1265 //
1266 // [Arguments]:
1267 //
1268 // [Return]:
1269 //
1270 //**************************************************************************
_mhal_mhl_GetEMSCTwoByteCRC(MS_U8 ucOpCode,MS_U8 ucValue)1271 MS_U8 _mhal_mhl_GetEMSCTwoByteCRC(MS_U8 ucOpCode, MS_U8 ucValue)
1272 {
1273 MS_U8 ucAValue = 0;
1274 MS_U8 ucBValue = 0;
1275 MS_U8 ucCValue = 0;
1276 MS_U16 ucCommand = BIT(13) |(((MS_U16)ucOpCode &BMASK(1:0)) << 11) |(((MS_U16)ucValue &BMASK(7:0)) << 3);
1277
1278 ucAValue = GET_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCommand &BIT(11)) +GET_BIT(ucCommand &BIT(8));
1279 ucAValue = ucAValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BIT(4)) +3;
1280 ucBValue = GET_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(10)) +GET_BIT(ucCommand &BIT(8));
1281 ucBValue = ucBValue +GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(3)) +2;
1282 ucCValue = GET_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCommand &BIT(9)) +GET_BIT(ucCommand &BIT(7));
1283 ucCValue = ucCValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +2;
1284
1285 if(ucAValue &BIT(0))
1286 {
1287 ucCommand |= BIT(2);
1288 }
1289
1290 if(ucBValue &BIT(0))
1291 {
1292 ucCommand |= BIT(1);
1293 }
1294
1295 if(ucCValue &BIT(0))
1296 {
1297 ucCommand |= BIT(0);
1298 }
1299
1300 return (ucCommand &BMASK(7:0));
1301 }
1302
1303 //**************************************************************************
1304 // [Function Name]:
1305 // _mhal_mhl_GetEMSCPayloadCRC()
1306 // [Description]
1307 //
1308 // [Arguments]:
1309 //
1310 // [Return]:
1311 //
1312 //**************************************************************************
_mhal_mhl_GetEMSCPayloadCRC(MS_U8 ucOpCode,MS_U16 usCRCValus)1313 MS_U16 _mhal_mhl_GetEMSCPayloadCRC(MS_U8 ucOpCode, MS_U16 usCRCValus)
1314 {
1315 MS_U8 ucAValue = 0;
1316 MS_U8 ucBValue = 0;
1317 MS_U8 ucCValue = GET_BIT(ucOpCode &BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(usCRCValus &BIT(6)) +GET_BIT(usCRCValus &BIT(7));
1318 MS_U8 ucDValue = GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(usCRCValus &BIT(5)) +GET_BIT(usCRCValus &BIT(6));
1319 MS_U8 ucEValue = GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(usCRCValus &BIT(4)) +GET_BIT(usCRCValus &BIT(5));
1320 MS_U8 ucFValue = GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(usCRCValus &BIT(3)) +GET_BIT(usCRCValus &BIT(4));
1321 MS_U8 ucGValue = GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3));
1322 MS_U8 ucHValue = GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2));
1323 MS_U8 ucIValue = GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(15));
1324 MS_U8 ucJValue = GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(14));
1325 MS_U8 ucKValue = GET_BIT(usCRCValus &BIT(13));
1326 MS_U8 ucLValue = GET_BIT(usCRCValus &BIT(12));
1327 MS_U8 ucMValue = GET_BIT(usCRCValus &BIT(11));
1328 MS_U8 ucNValue = GET_BIT(usCRCValus &BIT(10));
1329 MS_U8 ucOValue = GET_BIT(usCRCValus &BIT(9));
1330 MS_U8 ucPValue = 0;
1331 MS_U16 usCommand = 0;
1332
1333 ucAValue = GET_BIT(ucOpCode &BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0));
1334 ucAValue = ucAValue +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GET_BIT(usCRCValus &BIT(4)) +GET_BIT(usCRCValus &BIT(5)) +GET_BIT(usCRCValus &BIT(6)) +GET_BIT(usCRCValus &BIT(7));
1335 ucBValue = GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0));
1336 ucBValue = ucBValue +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GET_BIT(usCRCValus &BIT(4)) +GET_BIT(usCRCValus &BIT(5)) +GET_BIT(usCRCValus &BIT(6));
1337 ucPValue = ucAValue +GET_BIT(usCRCValus &BIT(8));
1338
1339 if(ucAValue &BIT(0))
1340 {
1341 usCommand |= BIT(15);
1342 }
1343
1344 if(ucBValue &BIT(0))
1345 {
1346 usCommand |= BIT(14);
1347 }
1348
1349 if(ucCValue &BIT(0))
1350 {
1351 usCommand |= BIT(13);
1352 }
1353
1354 if(ucDValue &BIT(0))
1355 {
1356 usCommand |= BIT(12);
1357 }
1358
1359 if(ucEValue &BIT(0))
1360 {
1361 usCommand |= BIT(11);
1362 }
1363
1364 if(ucFValue &BIT(0))
1365 {
1366 usCommand |= BIT(10);
1367 }
1368
1369 if(ucGValue &BIT(0))
1370 {
1371 usCommand |= BIT(9);
1372 }
1373
1374 if(ucHValue &BIT(0))
1375 {
1376 usCommand |= BIT(8);
1377 }
1378
1379 if(ucIValue &BIT(0))
1380 {
1381 usCommand |= BIT(7);
1382 }
1383
1384 if(ucJValue &BIT(0))
1385 {
1386 usCommand |= BIT(6);
1387 }
1388
1389 if(ucKValue &BIT(0))
1390 {
1391 usCommand |= BIT(5);
1392 }
1393
1394 if(ucLValue &BIT(0))
1395 {
1396 usCommand |= BIT(4);
1397 }
1398
1399 if(ucMValue &BIT(0))
1400 {
1401 usCommand |= BIT(3);
1402 }
1403
1404 if(ucNValue &BIT(0))
1405 {
1406 usCommand |= BIT(2);
1407 }
1408
1409 if(ucOValue &BIT(0))
1410 {
1411 usCommand |= BIT(1);
1412 }
1413
1414 if(ucPValue &BIT(0))
1415 {
1416 usCommand |= BIT(0);
1417 }
1418
1419 return usCommand;
1420 }
1421
1422 //**************************************************************************
1423 // [Function Name]:
1424 // _mhal_mhl_ECbusInitialSetting()
1425 // [Description]
1426 //
1427 // [Arguments]:
1428 //
1429 // [Return]:
1430 //
1431 //**************************************************************************
_mhal_mhl_ECbusInitialSetting(void)1432 void _mhal_mhl_ECbusInitialSetting(void)
1433 {
1434 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x35, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0]: deglitch after reorder
1435
1436 W2BYTEMSK(REG_MHL_ECBUS_PHY_4C, 0x8880, BMASK(15:4));
1437 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, 0x8B14, BMASK(15:1));
1438 W2BYTEMSK(REG_MHL_ECBUS_PHY_4E, 0x001C, BMASK(15:0));
1439 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, 0x0100, BMASK(15:0));
1440 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0200, BMASK(15:0));
1441 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); // [14:13]
1442 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13));
1443 W2BYTEMSK(REG_MHL_ECBUS_PHY_55, 0, BMASK(15:4)); //[7:0]
1444 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step
1445 W2BYTEMSK(REG_MHL_ECBUS_PHY_78, BIT(0), BIT(0));
1446
1447 W2BYTEMSK(REG_MHL_ECBUS_0E, 8, BMASK(4:0));
1448 W2BYTEMSK(REG_MHL_ECBUS_2D, BIT(3), BIT(3));
1449
1450 //auto reset turn on
1451 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en
1452 W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(4:3), BMASK(4:3)); // [4]:reg_rst_aft_fail_en, [3]:reg_rst_aft_clklck_en
1453
1454 // ECbus initial
1455 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7]
1456 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5));
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x06, BMASK(3:0)); // [11:8]:
1458 W2BYTEMSK(REG_MHL_ECBUS_PHY_68, 0x30, BMASK(6:4)); // [6:4]: pre-deglitch
1459 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x50, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0]: deglitch after reorder
1460 W2BYTEMSK(REG_MHL_ECBUS_PHY_65, 0x08, BMASK(5:0)); // [5:0]: reg_dat_lsb_mask; after analog rwa data deglicth,re-order,the lsb data 1 will be mask
1461
1462 //U02 ECO item setting
1463 W2BYTEMSK(REG_MHL_ECBUS_77, (_mhal_mhl_GetEMSCOneByteCRC(5) << 8)| _mhal_mhl_GetEMSCOneByteCRC(4), BMASK(15:0)); // [15:8]:EMSC neck, [7:0]:EMSC ack
1464 W2BYTEMSK(REG_MHL_ECBUS_78, (_mhal_mhl_GetEMSCOneByteCRC(7) << 8)| _mhal_mhl_GetEMSCOneByteCRC(6), BMASK(15:0)); // [15:8]:Dstart, [7:0]:grant
1465 W2BYTEMSK(REG_MHL_ECBUS_79, BIT(11)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 1) << 3)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 2) << 6), BIT(11)| BMASK(8:6)| BMASK(5:3)); // [8:6]:EMSC errsum cmd CRC, [5:3]:EMSC errCRC cmd CRC
1466 W2BYTEMSK(REG_MHL_ECBUS_PHY_13, BIT(4), BIT(4)); //
1467 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, BIT(11), BIT(11)); //
1468
1469 //eCBUS fsm timing
1470 W2BYTEMSK(REG_MHL_ECBUS_04, 0xE0E, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_sink_cal, [6:0]: reg_t_snk_cal 1; sink sends eCBUS clock after detecting eCBUS clock form source.
1471 W2BYTEMSK(REG_MHL_ECBUS_06, 0x1C00, BMASK(14:8)); // [14:8]: reg_t_snk_tdm;
1472 W2BYTEMSK(REG_MHL_ECBUS_03, BMASK(15:14), BMASK(15:14)); // [15]:reg_wait_tdm_timer_dis [14]:reg_wait_comma2_timer_dis
1473 W2BYTEMSK(REG_MHL_ECBUS_07, 0x104, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_snk_tdm;
1474 W2BYTEMSK(REG_MHL_ECBUS_3F, 0, BMASK(1:0)); //
1475 W2BYTEMSK(REG_MHL_ECBUS_48, 0, BMASK(2:0)); //
1476
1477 //clock detect setting
1478 W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock reference value
1479 W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock reference failure threshold range; [7:0]:reg_crlock_thr, the CR lock reference correct threshold range;
1480 W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock threshold; [4:0]:reg_cr_lock_num; CR lock success threshold time.
1481
1482 #if(MHL_ECBUS_AUTO_TRAINING)
1483 //auto training testing
1484 W2BYTEMSK(REG_MHL_ECBUS_PHY_5C, 0x010A, BMASK(15:0)); // [10:8]:reg_txloc_golden_lowr_tol, [5:0]:reg_txloc_golden_lower,
1485 W2BYTEMSK(REG_MHL_ECBUS_PHY_66, 0x2117, BMASK(15:0)); // [14:12]:reg_txloc_golden2_tol, [10:8]:reg_txloc_rev_golden_tol, [5:0]:reg_txloc_rev_golden
1486 W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_txloc_txdelay_add, [6:4]:reg_flow_retry_r, [2:0]:reg_flow_retry
1487 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time
1488 W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txloc_golden_tol, [5:0]:ret_txloc_golden
1489 #else
1490 // Skip atop training
1491 // REG_PM_MHL_CBUS2_4A [14]tx_rep_pd_ove = 1 [13]tx_rep_pd_ov [8]:tx_width_ove = 1 [7:4]:tx_width_ov
1492 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x33, BIT(8)| BMASK(7:4));
1493
1494 // REG_PM_MHL_CBUS2_4B ,[14]tx_pd_ove = 1 [13]tx_pd_ov [8]:tx_delay_ove = 1 [7:4]:tx_delay_ov
1495 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4));
1496
1497 //W2BYTEMSK(REG_MHL_ECBUS_PHY_6C, 0x8000, BMASK(15:8));
1498 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(8), BIT(8));
1499
1500 W2BYTEMSK(REG_MHL_ECBUS_PHY_6C, 0x0000, BMASK(15:0));
1501 //W2BYTEMSK(REG_MHL_ECBUS_04, (30 << 8), BMASK(14:8));
1502 #endif
1503 }
1504
1505 //**************************************************************************
1506 // [Function Name]:
1507 // _mhal_mhl_SetECbusStateChangeInterrupt()
1508 // [Description]
1509 //
1510 // [Arguments]:
1511 //
1512 // [Return]:
1513 //
1514 //**************************************************************************
_mhal_mhl_SetECbusStateChangeInterrupt(MS_BOOL bEnableFlag)1515 void _mhal_mhl_SetECbusStateChangeInterrupt(MS_BOOL bEnableFlag)
1516 {
1517 if(bEnableFlag)
1518 {
1519 W2BYTEMSK(REG_MHL_ECBUS_36, 0, BIT(0)); // Ecbus state change int mask
1520 }
1521 else
1522 {
1523 W2BYTEMSK(REG_MHL_ECBUS_36, BIT(0), BIT(0)); // Ecbus state change int mask
1524 }
1525
1526 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear
1527 }
1528
1529 //**************************************************************************
1530 // [Function Name]:
1531 // _mhal_mhl_SetEMSCReceiveInterrupt()
1532 // [Description]
1533 //
1534 // [Arguments]:
1535 //
1536 // [Return]:
1537 //
1538 //**************************************************************************
_mhal_mhl_SetEMSCReceiveInterrupt(MS_BOOL bEnableFlag)1539 void _mhal_mhl_SetEMSCReceiveInterrupt(MS_BOOL bEnableFlag)
1540 {
1541 W2BYTEMSK(REG_MHL_ECBUS_36, bEnableFlag? 0: BIT(12), BIT(12)); // eMSC receive int mask
1542 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear
1543 }
1544
1545 //**************************************************************************
1546 // [Function Name]:
1547 // _mhal_mhl_CbusConnectCheckEnable()
1548 // [Description]
1549 //
1550 // [Arguments]:
1551 //
1552 // [Return]:
1553 //
1554 //**************************************************************************
_mhal_mhl_CbusConnectCheckEnable(MS_BOOL bEnableFlag)1555 void _mhal_mhl_CbusConnectCheckEnable(MS_BOOL bEnableFlag)
1556 {
1557 W2BYTEMSK(REG_PM_MHL_CBUS_0B, bEnableFlag? MHL_CBUS_CONNECT_CHECK_VALUE: 0, BMASK(15:0)); // [15:0]: Disable connection check
1558 }
1559
1560 //**************************************************************************
1561 // [Function Name]:
1562 // _mhal_mhl_ECbusEnableSetting()
1563 // [Description]
1564 //
1565 // [Arguments]:
1566 //
1567 // [Return]:
1568 //
1569 //**************************************************************************
_mhal_mhl_ECbusEnableSetting(MS_BOOL bEnableFlag)1570 void _mhal_mhl_ECbusEnableSetting(MS_BOOL bEnableFlag)
1571 {
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, bEnableFlag? 0: BIT(0), BIT(0)); // ECbus PLL pd
1573 //W2BYTEMSK(REG_MHL_ECBUS_PHY_55, bEnableFlag? 0: BIT(14), BIT(14)); // Rx power down
1574 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); //
1575 W2BYTEMSK(REG_MHL_ECBUS_PHY_6F, bEnableFlag? BIT(8): 0, BIT(8)); // ECbus clock detect
1576 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, bEnableFlag? 0: BIT(13), BIT(13));
1577 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13));
1578
1579 if(bEnableFlag)
1580 {
1581 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(13), BIT(13)); // [13]: ECbus on
1582 }
1583 else
1584 {
1585 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off
1586 }
1587 }
1588
1589 //**************************************************************************
1590 // [Function Name]:
1591 // _mhal_mhl_ECbusDmuxEnable()
1592 // [Description]
1593 //
1594 // [Arguments]:
1595 //
1596 // [Return]:
1597 //
1598 //**************************************************************************
_mhal_mhl_ECbusDmuxEnable(MS_BOOL bEnableFlag)1599 void _mhal_mhl_ECbusDmuxEnable(MS_BOOL bEnableFlag)
1600 {
1601 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux
1602 }
1603
1604 //**************************************************************************
1605 // [Function Name]:
1606 // _mhal_mhl_CbusEngineReset()
1607 // [Description]
1608 //
1609 // [Arguments]:
1610 //
1611 // [Return]:
1612 //
1613 //**************************************************************************
_mhal_mhl_CbusEngineReset(void)1614 void _mhal_mhl_CbusEngineReset(void)
1615 {
1616 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(0), BIT(0));
1617 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(0));
1618 }
1619
1620 //**************************************************************************
1621 // [Function Name]:
1622 // _mhal_mhl_ECbusStateReset()
1623 // [Description]
1624 //
1625 // [Arguments]:
1626 //
1627 // [Return]:
1628 //
1629 //**************************************************************************
_mhal_mhl_ECbusStateReset(void)1630 void _mhal_mhl_ECbusStateReset(void)
1631 {
1632 W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(1:0), BMASK(1:0)); // ECbus state reset
1633 W2BYTEMSK(REG_MHL_ECBUS_00, 0, BMASK(1:0)); // ECbus state reset
1634 }
1635
1636 //**************************************************************************
1637 // [Function Name]:
1638 // _mhal_mhl_SetShortReadAddress()
1639 // [Description]
1640 //
1641 // [Arguments]:
1642 //
1643 // [Return]:
1644 //
1645 //**************************************************************************
_mhal_mhl_SetShortReadAddress(MS_BOOL bECbusEnable)1646 void _mhal_mhl_SetShortReadAddress(MS_BOOL bECbusEnable)
1647 {
1648 W2BYTEMSK(REG_MHL_CBUS_17, bECbusEnable? 0x7000: 0x0800, BMASK(15:8)); // [15:8]: reg_ddc_hdcp_short_read_address
1649
1650 bECbusEnableFlag = bECbusEnable;
1651 }
1652
1653 //**************************************************************************
1654 // [Function Name]:
1655 // _mhal_mhl_Version3PhyEnable()
1656 // [Description]
1657 //
1658 // [Arguments]:
1659 //
1660 // [Return]:
1661 //
1662 //**************************************************************************
_mhal_mhl_Version3PhyEnable(MS_U8 ucCbusSelect,MS_BOOL bEnableFlag)1663 void _mhal_mhl_Version3PhyEnable(MS_U8 ucCbusSelect, MS_BOOL bEnableFlag)
1664 {
1665 switch(ucCbusSelect)
1666 {
1667 #if(MHL_FUNCTION_SUPPORT_PORTA)
1668 case MHL_CBUS_SELECT_PORTA:
1669 if(GET_MHL_PATH_SUPPORT_PORTA())
1670 {
1671 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engine enable
1672 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
1673 W2BYTEMSK(REG_COMBO_PHY0_P0_60_L, bEnableFlag? 0: BIT(5), BIT(5));
1674 }
1675
1676 break;
1677 #endif
1678
1679 #if(MHL_FUNCTION_SUPPORT_PORTB)
1680 case MHL_CBUS_SELECT_PORTB:
1681 if(GET_MHL_PATH_SUPPORT_PORTB())
1682 {
1683 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engine enable
1684 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
1685 W2BYTEMSK(REG_COMBO_PHY0_P1_60_L, bEnableFlag? 0: BIT(5), BIT(5));
1686 }
1687
1688 break;
1689 #endif
1690
1691 #if(MHL_FUNCTION_SUPPORT_PORTC)
1692 case MHL_CBUS_SELECT_PORTC:
1693 if(GET_MHL_PATH_SUPPORT_PORTC())
1694 {
1695 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engine enable
1696 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
1697 W2BYTEMSK(REG_COMBO_PHY0_P2_60_L, bEnableFlag? 0: BIT(5), BIT(5));
1698 }
1699
1700 break;
1701 #endif
1702
1703 #if(MHL_FUNCTION_SUPPORT_PORTD)
1704 case MHL_CBUS_SELECT_PORTD:
1705 if(GET_MHL_PATH_SUPPORT_PORTD())
1706 {
1707 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engine enable
1708 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
1709 W2BYTEMSK(REG_COMBO_PHY0_P3_60_L, bEnableFlag? 0: BIT(5), BIT(5));
1710 }
1711
1712 break;
1713 #endif
1714
1715 default:
1716
1717 break;
1718 };
1719 }
1720
1721 //**************************************************************************
1722 // [Function Name]:
1723 // _mhal_mhl_ECbusStateChangeProc()
1724 // [Description]
1725 //
1726 // [Arguments]:
1727 //
1728 // [Return]:
1729 //
1730 //**************************************************************************
_mhal_mhl_ECbusStateChangeProc(void)1731 void _mhal_mhl_ECbusStateChangeProc(void)
1732 {
1733 MS_U8 ucECbusState = (R2BYTE(REG_MHL_ECBUS_03) &0xF0) >> 4; // [7:4]: ECbus state
1734
1735 if(ucECbusState != ucECbusTrainState)
1736 {
1737 if(ucECbusState == MHL_ECBUS_STATE_WAIT_CLOCK_LOCK)
1738 {
1739 //W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, 0, BIT(0)); // [0]: ECbus PLL pd
1740 }
1741 else if(ucECbusState == MHL_ECBUS_STATE_WAIT_SEND_CLOCK)
1742 {
1743 if(R2BYTE(REG_MHL_ECBUS_PHY_4D) & BIT(15))
1744 {
1745 //_mhal_mhl_ECbusDmuxEnable(TRUE);
1746 }
1747
1748 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]
1749 }
1750 else if(ucECbusState == MHL_ECBUS_STATE_SOURCE_ACTIVE)
1751 {
1752
1753 }
1754 else if(ucECbusState == MHL_ECBUS_STATE_ACTIVE)
1755 {
1756
1757 }
1758 else if(ucECbusState == MHL_ECBUS_STATE_FAIL)
1759 {
1760 //_mhal_mhl_ECbusDmuxEnable(FALSE);
1761
1762 //W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0207, BMASK(15:0)); //
1763 #if(MHL_ECBUS_AUTO_TRAINING)
1764 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));//
1765 #endif
1766 //W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, BIT(0), BIT(0)); // [0]: ECbus PLL pd
1767 #if(MHL_ECBUS_AUTO_TRAINING)
1768 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay
1769 #endif
1770
1771 _mhal_mhl_ECbusStateReset();
1772
1773 ucECbusTrainFailCount++;
1774 }
1775
1776 ucECbusTrainState = ucECbusState;
1777 }
1778 }
1779
1780 //**************************************************************************
1781 // [Function Name]:
1782 // _mhal_mhl_ECbusModeUpProc()
1783 // [Description]
1784 //
1785 // [Arguments]:
1786 //
1787 // [Return]:
1788 //
1789 //**************************************************************************
_mhal_mhl_ECbusModeUpProc(void)1790 void _mhal_mhl_ECbusModeUpProc(void)
1791 {
1792 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status
1793 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status
1794
1795 //W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0207, BMASK(15:0));
1796 #if(MHL_ECBUS_AUTO_TRAINING)
1797 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));
1798 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay
1799 #endif
1800 }
1801
1802 //**************************************************************************
1803 // [Function Name]:
1804 // _mhal_mhl_ECbusModeDownProc()
1805 // [Description]
1806 //
1807 // [Arguments]:
1808 //
1809 // [Return]:
1810 //
1811 //**************************************************************************
_mhal_mhl_ECbusModeDownProc(void)1812 void _mhal_mhl_ECbusModeDownProc(void)
1813 {
1814 //W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0207, BMASK(15:0));
1815 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));
1816 }
1817
1818 //**************************************************************************
1819 // [Function Name]:
1820 // _mhal_mhl_MHL3MuxSetting0()
1821 // [Description]
1822 //
1823 // [Arguments]:
1824 //
1825 // [Return]:
1826 //
1827 //**************************************************************************
_mhal_mhl_MHL3MuxSetting0(MS_BOOL bLinkRate6GFlag)1828 void _mhal_mhl_MHL3MuxSetting0(MS_BOOL bLinkRate6GFlag)
1829 {
1830 W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_case
1831 }
1832
1833 //**************************************************************************
1834 // [Function Name]:
1835 // _mhal_mhl_GetSRAMReceiveEMSCData()
1836 // [Description]
1837 //
1838 // [Arguments]:
1839 //
1840 // [Return]:
1841 //
1842 //**************************************************************************
_mhal_mhl_GetSRAMReceiveEMSCData(void)1843 MS_U8 _mhal_mhl_GetSRAMReceiveEMSCData(void)
1844 {
1845 W2BYTEMSK(REG_MHL_ECBUS_23, BIT(15), BIT(15));
1846
1847 while((R2BYTE(REG_MHL_ECBUS_23) & BIT(14)) == BIT(14));
1848
1849 return (R2BYTE(REG_MHL_ECBUS_22) &BMASK(7:0));
1850 }
1851
1852 //**************************************************************************
1853 // [Function Name]:
1854 // _mhal_mhl_GetSRAMReceiveEMSCData()
1855 // [Description]
1856 //
1857 // [Arguments]:
1858 //
1859 // [Return]:
1860 //
1861 //**************************************************************************
_mhal_mhl_InsertSRAMSendEMSCData(MS_U8 ucSendEMSC)1862 void _mhal_mhl_InsertSRAMSendEMSCData(MS_U8 ucSendEMSC)
1863 {
1864 W2BYTEMSK(REG_MHL_ECBUS_20, ucSendEMSC, BMASK(7:0));
1865
1866 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15));
1867
1868 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14));
1869 }
1870
1871 #if(MHL_ECBUS_COMMAND_PARSING)
1872 //**************************************************************************
1873 // [Function Name]:
1874 // _mhal_mhl_ParsingECbusCommand()
1875 // [Description]
1876 //
1877 // [Arguments]:
1878 //
1879 // [Return]:
1880 //
1881 //**************************************************************************
_mhal_mhl_ParsingECbusCommand(MS_U16 * usECbusData)1882 void _mhal_mhl_ParsingECbusCommand(MS_U16 *usECbusData)
1883 {
1884 MS_U8 ucTimes = 0;
1885 MS_U16 ustemp = 0;
1886 MS_U16 usCounnter = 0;
1887 MS_U16 usValue = 0;
1888
1889 for(ustemp = 0; ustemp < MHL_BUFFER_ECBUS_DATA_LENGTH; ustemp++)
1890 {
1891 if((usECbusData[ustemp] &BMASK(7:0)) == 0x39) // Find CBUS1_START
1892 {
1893 ucTimes = 0;
1894
1895 if(usECbusData[ustemp] &BIT(15)) // Send case
1896 {
1897 for(usCounnter = ustemp +1; usCounnter < MHL_BUFFER_ECBUS_DATA_LENGTH; usCounnter++)
1898 {
1899 if(usECbusData[usCounnter] &BIT(15))
1900 {
1901 usValue = usValue << 8;
1902 usValue = usValue |(usECbusData[usCounnter] &BMASK(7:0));
1903
1904 ucTimes++;
1905 }
1906
1907 if(ucTimes == 2)
1908 {
1909 usValue = usValue >> 5;
1910 ucTimes = usValue >> 8;
1911
1912 if(ucTimes == 5)
1913 {
1914 msg_mhl(printf(" MHL [SK][MSC][C] = %x\r\n", (usValue &BMASK(7:0))));
1915 }
1916 else if(ucTimes == 4)
1917 {
1918 msg_mhl(printf(" MHL [SK][MSC][D] = %x\r\n", (usValue &BMASK(7:0))));
1919 }
1920 else if(ucTimes == 1)
1921 {
1922 msg_mhl(printf(" MHL [SK][DDC][C] = %x\r\n", (usValue &BMASK(7:0))));
1923 }
1924 else if(ucTimes == 0)
1925 {
1926 msg_mhl(printf(" MHL [SK][DDC][D] = %x\r\n", (usValue &BMASK(7:0))));
1927 }
1928 else
1929 {
1930 msg_mhl(printf(" MHL [SK] unknow = %x\r\n", (usValue &BMASK(7:0))));
1931 }
1932
1933 break;
1934 }
1935 }
1936 }
1937 else // Receive case
1938 {
1939 for(usCounnter = ustemp +1; usCounnter < MHL_BUFFER_ECBUS_DATA_LENGTH; usCounnter++)
1940 {
1941 if((usECbusData[usCounnter] &BIT(15)) == 0)
1942 {
1943 usValue = usValue << 8;
1944 usValue = usValue |(usECbusData[usCounnter] &BMASK(7:0));
1945
1946 ucTimes++;
1947 }
1948
1949 if(ucTimes == 2)
1950 {
1951 usValue = usValue >> 5;
1952 ucTimes = usValue >> 8;
1953
1954 if(ucTimes == 5)
1955 {
1956 msg_mhl(printf(" MHL [SO][MSC][C] = %x\r\n", (usValue &BMASK(7:0))));
1957 }
1958 else if(ucTimes == 4)
1959 {
1960 msg_mhl(printf(" MHL [SO][MSC][D] = %x\r\n", (usValue &BMASK(7:0))));
1961 }
1962 else if(ucTimes == 1)
1963 {
1964 msg_mhl(printf(" MHL [SO][DDC][C] = %x\r\n", (usValue &BMASK(7:0))));
1965 }
1966 else if(ucTimes == 0)
1967 {
1968 msg_mhl(printf(" MHL [SO][DDC][D] = %x\r\n", (usValue &BMASK(7:0))));
1969 }
1970 else
1971 {
1972 msg_mhl(printf(" MHL [SO] unknow = %x\r\n", (usValue &BMASK(7:0))));
1973 }
1974
1975 break;
1976 }
1977 }
1978 }
1979 }
1980 }
1981 }
1982
1983 //**************************************************************************
1984 // [Function Name]:
1985 // _mhal_mhl_GetECbusCommand()
1986 // [Description]
1987 //
1988 // [Arguments]:
1989 //
1990 // [Return]:
1991 //
1992 //**************************************************************************
_mhal_mhl_GetECbusCommand(void)1993 void _mhal_mhl_GetECbusCommand(void)
1994 {
1995 MS_BOOL bReDoFlag = TRUE;
1996 MS_U8 ucReceiveData = 0;
1997 MS_U8 ucPreReceiveData = 0;
1998 MS_U8 ucSendData = 0;
1999 MS_U8 ucPreSendData = 0;
2000 MS_U16 usECbusCData[MHL_BUFFER_ECBUS_DATA_LENGTH] = {0};
2001 MS_U16 ustemp = 0;
2002 MS_U16 usCounnter = 0;
2003 static MS_U32 ulTimeout = 0;
2004
2005 if(ulTimeout < 40000000)
2006 {
2007 do
2008 {
2009 ucReceiveData = (R2BYTE(REG_MHL_ECBUS_7C) &BMASK(7:0));
2010 ucSendData = (R2BYTE(REG_MHL_ECBUS_7C) >>8);
2011
2012 if((ucReceiveData != 0x5A) && (ucPreReceiveData != ucReceiveData))
2013 {
2014 usECbusCData[ustemp] = ucReceiveData;
2015 ustemp++;
2016
2017 //msg_mhl(printf(" MHL receive data = %x, %d\r\n", ucReceiveData, ustemp));
2018
2019 ucPreReceiveData = ucReceiveData;
2020 bReDoFlag = TRUE;
2021 usCounnter = 0;
2022 }
2023
2024 if((ucSendData != 0x5A)&& (ucPreSendData != ucSendData))
2025 {
2026 usECbusCData[ustemp] = ucSendData |BIT(15);
2027 ustemp++;
2028
2029 //msg_mhl(printf(" MHL send data = %x, %d\r\n", ucSendData, ustemp));
2030
2031 ucPreSendData = ucSendData;
2032 bReDoFlag = TRUE;
2033 usCounnter = 0;
2034 }
2035
2036 if(ustemp == MHL_BUFFER_ECBUS_DATA_LENGTH)
2037 {
2038 bReDoFlag = FALSE;
2039
2040 for(usCounnter = 0; usCounnter < MHL_BUFFER_ECBUS_DATA_LENGTH; usCounnter++)
2041 {
2042 msg_mhl(printf(" MHL DDC data = %x\r\n", usECbusCData[usCounnter]));
2043 }
2044
2045 ustemp = 0;
2046
2047 _mhal_mhl_ParsingECbusCommand(usECbusCData);
2048 }
2049
2050 if(ulTimeout < 40000000)
2051 {
2052 ulTimeout++;
2053 }
2054 else
2055 {
2056 for(usCounnter = 0; usCounnter < ustemp; usCounnter++)
2057 {
2058 msg_mhl(printf(" MHL DDC data = %x\r\n", usECbusCData[usCounnter]));
2059 }
2060
2061 bReDoFlag = FALSE;
2062 ustemp = 0;
2063
2064 _mhal_mhl_ParsingECbusCommand(usECbusCData);
2065 }
2066 }while(bReDoFlag);
2067 }
2068 }
2069
2070 #endif
2071
2072 //-------------------------------------------------------------------------------------------------
2073 // Global Functions
2074 //-------------------------------------------------------------------------------------------------
2075
2076 //**************************************************************************
2077 // [Function Name]:
2078 // mhal_mhl_GetCbusSelect()
2079 // [Description]
2080 //
2081 // [Arguments]:
2082 //
2083 // [Return]:
2084 //
2085 //**************************************************************************
mhal_mhl_GetCbusSelect(MS_U8 ucPort)2086 MS_U8 mhal_mhl_GetCbusSelect(MS_U8 ucPort)
2087 {
2088 MS_U8 uctemp = MHL_CBUS_SELECT_MASK;
2089
2090 switch(ucPort)
2091 {
2092 case MHL_DVI_PORT_A:
2093 uctemp = MHL_CBUS_SELECT_PORTA;
2094 break;
2095
2096 case MHL_DVI_PORT_B:
2097 uctemp = MHL_CBUS_SELECT_PORTB;
2098 break;
2099
2100 case MHL_DVI_PORT_C:
2101 uctemp = MHL_CBUS_SELECT_PORTC;
2102 break;
2103
2104 default:
2105
2106 break;
2107 };
2108
2109 return uctemp;
2110 }
2111
2112 //**************************************************************************
2113 // [Function Name]:
2114 // mhal_mhl_GetInputPort()
2115 // [Description]
2116 // MHL get current input port
2117 // [Arguments]:
2118 //
2119 // [Return]:
2120 //
2121 //**************************************************************************
mhal_mhl_GetInputPort(void)2122 MS_U8 mhal_mhl_GetInputPort(void)
2123 {
2124 return (R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0));
2125 }
2126
2127 //**************************************************************************
2128 // [Function Name]:
2129 // mhal_mhl_CheckInputPort()
2130 // [Description]
2131 // MHL check current input port
2132 // [Arguments]:
2133 //
2134 // [Return]:
2135 //
2136 //**************************************************************************
mhal_mhl_CheckInputPort(MS_U8 ucCbusSelect)2137 MS_BOOL mhal_mhl_CheckInputPort(MS_U8 ucCbusSelect)
2138 {
2139 MS_BOOL bindex = FALSE;
2140
2141 if(mhal_mhl_GetCbusSelect(mhal_mhl_GetInputPort()) == ucCbusSelect)
2142 {
2143 bindex = TRUE;
2144 }
2145
2146 return bindex;
2147 }
2148
2149 //**************************************************************************
2150 // [Function Name]:
2151 // mhal_mhl_CheckPIPWindow()
2152 // [Description]
2153 //
2154 // [Arguments]:
2155 //
2156 // [Return]:
2157 //
2158 //**************************************************************************
mhal_mhl_CheckPIPWindow(void)2159 MS_BOOL mhal_mhl_CheckPIPWindow(void)
2160 {
2161 MS_BOOL bFlag = FALSE;
2162 MS_U8 ucScalerMainMux = R2BYTE(0x102E02) &BMASK(7:0);
2163 MS_U8 ucScalerSubMux = ucScalerMainMux &BMASK(3:0);
2164
2165 ucScalerMainMux = (ucScalerMainMux &BMASK(7:4)) >> 4;
2166
2167 if((ucScalerMainMux == MHL_SCALER_MUX_SELECT_DVI) || (ucScalerSubMux == MHL_SCALER_MUX_SELECT_DVI))
2168 {
2169 bFlag = TRUE;
2170 }
2171
2172 return bFlag;
2173 }
2174
2175 //**************************************************************************
2176 // [Function Name]:
2177 // mhal_mhl_MHLSupportPath()
2178 // [Description]
2179 // MHL support path
2180 // [Arguments]:
2181 //
2182 // [Return]:
2183 //
2184 //**************************************************************************
mhal_mhl_MHLSupportPath(MS_U8 ucSelect)2185 void mhal_mhl_MHLSupportPath(MS_U8 ucSelect)
2186 {
2187 ucMHLSupportPort = ucSelect;
2188 }
2189
2190 //**************************************************************************
2191 // [Function Name]:
2192 // mhal_mhl_CheckEfuseControlFlag()
2193 // [Description]
2194 //
2195 // [Arguments]:
2196 //
2197 // [Return]:
2198 //
2199 //**************************************************************************
mhal_mhl_CheckEfuseControlFlag(MS_BOOL bEfuseFlag)2200 MS_BOOL mhal_mhl_CheckEfuseControlFlag(MS_BOOL bEfuseFlag)
2201 {
2202 MS_BOOL bFlag = FALSE;
2203
2204 #if(MHL_EFUSE_FUNCTION_CONTROL)
2205 MS_U8 uctemp = 0;
2206
2207 if(!bEfuseFlag)
2208 {
2209 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
2210 {
2211 mhal_mhl_CbusIsolate(uctemp, TRUE);
2212 }
2213
2214 bFlag = TRUE;
2215 }
2216
2217 #endif
2218
2219 return bFlag;
2220 }
2221
2222 //**************************************************************************
2223 // [Function Name]:
2224 // mhal_mhl_InsertChipIDforCheck()
2225 // [Description]
2226 //
2227 // [Arguments]:
2228 //
2229 // [Return]:
2230 //
2231 //**************************************************************************
mhal_mhl_InsertChipIDforCheck(MS_U8 ucChipID)2232 void mhal_mhl_InsertChipIDforCheck(MS_U8 ucChipID)
2233 {
2234 ucChipIDValue = ucChipID;
2235
2236 msg_mhl(printf("** MHL Cbus index value %x\r\n", ucChipID));
2237 }
2238
2239 //**************************************************************************
2240 // [Function Name]:
2241 // mhal_mhl_CbusSelectSetMux()
2242 // [Description]
2243 //
2244 // [Arguments]:
2245 //
2246 // [Return]:
2247 //
2248 //**************************************************************************
mhal_mhl_CbusSelectSetMux(MS_U8 ucCbusSelect)2249 void mhal_mhl_CbusSelectSetMux(MS_U8 ucCbusSelect)
2250 {
2251 switch(ucCbusSelect)
2252 {
2253 #if(MHL_FUNCTION_SUPPORT_PORTA)
2254 case MHL_CBUS_SELECT_PORTA:
2255 if(GET_MHL_PATH_SUPPORT_PORTA())
2256 {
2257
2258 }
2259
2260 break;
2261 #endif
2262
2263 #if(MHL_FUNCTION_SUPPORT_PORTB)
2264 case MHL_CBUS_SELECT_PORTB:
2265 if(GET_MHL_PATH_SUPPORT_PORTB())
2266 {
2267
2268 }
2269
2270 break;
2271 #endif
2272
2273 #if(MHL_FUNCTION_SUPPORT_PORTC)
2274 case MHL_CBUS_SELECT_PORTC:
2275 if(GET_MHL_PATH_SUPPORT_PORTC())
2276 {
2277
2278 }
2279
2280 break;
2281 #endif
2282
2283 #if(MHL_FUNCTION_SUPPORT_PORTD)
2284 case MHL_CBUS_SELECT_PORTD:
2285 if(GET_MHL_PATH_SUPPORT_PORTD())
2286 {
2287
2288 }
2289
2290 break;
2291 #endif
2292
2293 default:
2294
2295 break;
2296 };
2297 }
2298
2299 //**************************************************************************
2300 // [Function Name]:
2301 // mhal_mhl_CableDetect()
2302 // [Description]
2303 // MHL cable detection
2304 // [Arguments]:
2305 //
2306 // [Return]:
2307 // TRUE: MHL cable plugged
2308 // FALSE: MHL cable unplugged
2309 //**************************************************************************
mhal_mhl_CableDetect(MS_U8 ucCbusSelect)2310 MS_BOOL mhal_mhl_CableDetect(MS_U8 ucCbusSelect)
2311 {
2312 MS_BOOL bFlag = FALSE;
2313
2314 switch(ucCbusSelect)
2315 {
2316 #if(MHL_FUNCTION_SUPPORT_PORTA)
2317 case MHL_CBUS_SELECT_PORTA:
2318 if(GET_MHL_PATH_SUPPORT_PORTA())
2319 {
2320 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
2321 }
2322
2323 break;
2324 #endif
2325
2326 #if(MHL_FUNCTION_SUPPORT_PORTB)
2327 case MHL_CBUS_SELECT_PORTB:
2328 if(GET_MHL_PATH_SUPPORT_PORTB())
2329 {
2330
2331 }
2332
2333 break;
2334 #endif
2335
2336 #if(MHL_FUNCTION_SUPPORT_PORTC)
2337 case MHL_CBUS_SELECT_PORTC:
2338 if(GET_MHL_PATH_SUPPORT_PORTC())
2339 {
2340 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
2341 }
2342
2343 break;
2344 #endif
2345
2346 #if(MHL_FUNCTION_SUPPORT_PORTD)
2347 case MHL_CBUS_SELECT_PORTD:
2348 if(GET_MHL_PATH_SUPPORT_PORTD())
2349 {
2350 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
2351 }
2352
2353 break;
2354 #endif
2355
2356 default:
2357
2358 break;
2359 };
2360
2361 return bFlag;
2362 }
2363
2364 //**************************************************************************
2365 // [Function Name]:
2366 // mhal_mhl_Accumulator_Clr()
2367 // [Description]
2368 // to clear accumulator when input is not MHL
2369 // [Arguments]:
2370 //
2371 // [Return]:
2372 //**************************************************************************
mhal_mhl_Accumulator_Clr(MS_U8 ucCbusSelect)2373 void mhal_mhl_Accumulator_Clr(MS_U8 ucCbusSelect)
2374 {
2375 switch(ucCbusSelect)
2376 {
2377 #if(MHL_FUNCTION_SUPPORT_PORTA)
2378 case MHL_CBUS_SELECT_PORTA:
2379 if(GET_MHL_PATH_SUPPORT_PORTA())
2380 {
2381
2382 }
2383
2384 break;
2385 #endif
2386
2387 #if(MHL_FUNCTION_SUPPORT_PORTB)
2388 case MHL_CBUS_SELECT_PORTB:
2389 if(GET_MHL_PATH_SUPPORT_PORTB())
2390 {
2391
2392 }
2393
2394 break;
2395 #endif
2396
2397 #if(MHL_FUNCTION_SUPPORT_PORTC)
2398 case MHL_CBUS_SELECT_PORTC:
2399 if(GET_MHL_PATH_SUPPORT_PORTC())
2400 {
2401
2402 }
2403
2404 break;
2405 #endif
2406
2407 #if(MHL_FUNCTION_SUPPORT_PORTD)
2408 case MHL_CBUS_SELECT_PORTD:
2409 if(GET_MHL_PATH_SUPPORT_PORTD())
2410 {
2411
2412 }
2413
2414 break;
2415 #endif
2416
2417 default:
2418
2419 break;
2420 };
2421 }
2422
2423 //**************************************************************************
2424 // [Function Name]:
2425 // mhal_mhl_CDRModeMonitor()
2426 // [Description]:
2427 // MHL CDR mode monitor
2428 // [Arguments]:
2429 // isCbusConnected: Cbus is at connected state or not
2430 // [Return]:
2431 //
2432 //**************************************************************************
mhal_mhl_CDRModeMonitor(MS_U8 ucCbusSelect,MS_BOOL bPathEnable)2433 MS_BOOL mhal_mhl_CDRModeMonitor(MS_U8 ucCbusSelect, MS_BOOL bPathEnable)
2434 {
2435 MS_BOOL bindex = FALSE;
2436 static MS_U8 ucStableCount = 0;
2437 static MS_BOOL bPLLPower[MHL_CBUS_SELECT_MASK] = {TRUE, TRUE, TRUE};
2438
2439 switch(ucCbusSelect)
2440 {
2441 #if(MHL_FUNCTION_SUPPORT_PORTA)
2442 case MHL_CBUS_SELECT_PORTA:
2443 if(GET_MHL_PATH_SUPPORT_PORTA())
2444 {
2445 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
2446 {
2447 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
2448 {
2449 ucStableCount++;
2450 }
2451
2452 if(!bPLLPower[ucCbusSelect])
2453 {
2454 bPLLPower[ucCbusSelect] = TRUE;
2455 }
2456
2457 if((R2BYTE(REG_DVI_DTOP_DUAL_P0_31_L) &BIT(6)) == BIT(6)) // DE stable
2458 {
2459 if(ucStableCount < MHL_CDR_STABLE_THRESHOLD)
2460 {
2461 ucStableCount = MHL_CDR_STABLE_THRESHOLD;
2462 }
2463 else if(ucStableCount == (MHL_CDR_FORCE_THRESHOLD -1))
2464 {
2465 if(bECbusEnableFlag)
2466 {
2467 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, BIT(13), BIT(13));
2468 //MsOS_DelayTaskUs(1);
2469 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, 0, BIT(13));
2470
2471 msg_mhl(printf("** MHL toggle ~~~\r\n"));
2472 }
2473 }
2474 }
2475 else // DE unstable
2476 {
2477 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
2478 {
2479 ucStableCount = 0;
2480 }
2481 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -1))
2482 {
2483 msg_mhl(printf("** MHL time change toggle CDR mode\r\n"));
2484
2485 ucStableCount = 0;
2486 }
2487 }
2488 }
2489 else
2490 {
2491 if(bPLLPower[ucCbusSelect])
2492 {
2493 bPLLPower[ucCbusSelect] = FALSE;
2494 ucStableCount = 0;
2495 }
2496 }
2497 }
2498
2499 break;
2500 #endif
2501
2502 #if(MHL_FUNCTION_SUPPORT_PORTB)
2503 case MHL_CBUS_SELECT_PORTB:
2504 if(GET_MHL_PATH_SUPPORT_PORTB())
2505 {
2506 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
2507 {
2508 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
2509 {
2510 ucStableCount++;
2511 }
2512
2513 if(!bPLLPower[ucCbusSelect])
2514 {
2515 bPLLPower[ucCbusSelect] = TRUE;
2516 }
2517
2518 if((R2BYTE(REG_DVI_DTOP_DUAL_P1_31_L) &BIT(6)) == BIT(6)) // DE stable
2519 {
2520 if(ucStableCount < MHL_CDR_STABLE_THRESHOLD)
2521 {
2522 ucStableCount = MHL_CDR_STABLE_THRESHOLD;
2523 }
2524 else if(ucStableCount == (MHL_CDR_FORCE_THRESHOLD -1))
2525 {
2526 if(bECbusEnableFlag)
2527 {
2528 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, BIT(13), BIT(13));
2529 //MsOS_DelayTaskUs(1);
2530 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, 0, BIT(13));
2531
2532 msg_mhl(printf("** MHL toggle ~~~\r\n"));
2533 }
2534 }
2535 }
2536 else // DE unstable
2537 {
2538 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
2539 {
2540 ucStableCount = 0;
2541 }
2542 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -1))
2543 {
2544 msg_mhl(printf("** MHL time change toggle CDR mode\r\n"));
2545
2546 ucStableCount = 0;
2547 }
2548 }
2549 }
2550 else
2551 {
2552 if(bPLLPower[ucCbusSelect])
2553 {
2554 bPLLPower[ucCbusSelect] = FALSE;
2555 ucStableCount = 0;
2556 }
2557 }
2558 }
2559
2560 break;
2561 #endif
2562
2563 #if(MHL_FUNCTION_SUPPORT_PORTC)
2564 case MHL_CBUS_SELECT_PORTC:
2565 if(GET_MHL_PATH_SUPPORT_PORTC())
2566 {
2567 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
2568 {
2569 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
2570 {
2571 ucStableCount++;
2572 }
2573
2574 if(!bPLLPower[ucCbusSelect])
2575 {
2576 bPLLPower[ucCbusSelect] = TRUE;
2577 }
2578
2579 if((R2BYTE(REG_DVI_DTOP_DUAL_P2_31_L) &BIT(6)) == BIT(6)) // DE stable
2580 {
2581 if(ucStableCount < MHL_CDR_STABLE_THRESHOLD)
2582 {
2583 ucStableCount = MHL_CDR_STABLE_THRESHOLD;
2584 }
2585 else if(ucStableCount == (MHL_CDR_FORCE_THRESHOLD -1))
2586 {
2587 if(bECbusEnableFlag)
2588 {
2589 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, BIT(13), BIT(13));
2590 //MsOS_DelayTaskUs(1);
2591 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, 0, BIT(13));
2592
2593 msg_mhl(printf("** MHL toggle ~~~\r\n"));
2594 }
2595 }
2596 }
2597 else // DE unstable
2598 {
2599 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
2600 {
2601 ucStableCount = 0;
2602 }
2603 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -1))
2604 {
2605 msg_mhl(printf("** MHL time change toggle CDR mode\r\n"));
2606
2607 ucStableCount = 0;
2608 }
2609 }
2610 }
2611 else
2612 {
2613 if(bPLLPower[ucCbusSelect])
2614 {
2615 bPLLPower[ucCbusSelect] = FALSE;
2616 ucStableCount = 0;
2617 }
2618 }
2619 }
2620
2621 break;
2622 #endif
2623
2624 #if(MHL_FUNCTION_SUPPORT_PORTD)
2625 case MHL_CBUS_SELECT_PORTD:
2626 if(GET_MHL_PATH_SUPPORT_PORTD())
2627 {
2628 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
2629 {
2630 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
2631 {
2632 ucStableCount++;
2633 }
2634
2635 if(!bPLLPower[ucCbusSelect])
2636 {
2637 bPLLPower[ucCbusSelect] = TRUE;
2638 }
2639
2640 if((R2BYTE(REG_DVI_DTOP_DUAL_P3_31_L) &BIT(6)) == BIT(6)) // DE stable
2641 {
2642 if(ucStableCount < MHL_CDR_STABLE_THRESHOLD)
2643 {
2644 ucStableCount = MHL_CDR_STABLE_THRESHOLD;
2645 }
2646 else if(ucStableCount == (MHL_CDR_FORCE_THRESHOLD -1))
2647 {
2648 if(bECbusEnableFlag)
2649 {
2650 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, BIT(13), BIT(13));
2651 //MsOS_DelayTaskUs(1);
2652 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, 0, BIT(13));
2653
2654 msg_mhl(printf("** MHL toggle ~~~\r\n"));
2655 }
2656 }
2657 }
2658 else // DE unstable
2659 {
2660 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
2661 {
2662 ucStableCount = 0;
2663 }
2664 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -1))
2665 {
2666 msg_mhl(printf("** MHL time change toggle CDR mode\r\n"));
2667
2668 ucStableCount = 0;
2669 }
2670 }
2671 }
2672 else
2673 {
2674 if(bPLLPower[ucCbusSelect])
2675 {
2676 bPLLPower[ucCbusSelect] = FALSE;
2677 ucStableCount = 0;
2678 }
2679 }
2680 }
2681
2682 break;
2683 #endif
2684
2685 default:
2686
2687 break;
2688 };
2689
2690 if(ucStableCount >= MHL_CDR_FORCE_THRESHOLD)
2691 {
2692 bMHLSignalStable = TRUE;
2693 }
2694 else if(bMHLSignalStable)
2695 {
2696 bMHLSignalStable = FALSE;
2697 }
2698
2699 return bindex;
2700 }
2701
2702 //**************************************************************************
2703 // [Function Name]:
2704 // mhal_mhl_CbusIsolate()
2705 // [Description]
2706 // MHL cable isolate
2707 // [Arguments]:
2708 //
2709 // [Return]:
2710 //
2711 //**************************************************************************
mhal_mhl_CbusIsolate(MS_U8 ucCbusSelect,MS_BOOL bFlag)2712 void mhal_mhl_CbusIsolate(MS_U8 ucCbusSelect, MS_BOOL bFlag)
2713 {
2714 switch(ucCbusSelect)
2715 {
2716 #if(MHL_FUNCTION_SUPPORT_PORTA)
2717 case MHL_CBUS_SELECT_PORTA:
2718 if(GET_MHL_PATH_SUPPORT_PORTA())
2719 {
2720 if(bFlag)
2721 {
2722 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
2723 }
2724 else
2725 {
2726 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
2727 }
2728 }
2729
2730 break;
2731 #endif
2732
2733 #if(MHL_FUNCTION_SUPPORT_PORTB)
2734 case MHL_CBUS_SELECT_PORTB:
2735 if(GET_MHL_PATH_SUPPORT_PORTB())
2736 {
2737
2738 }
2739
2740 break;
2741 #endif
2742
2743 #if(MHL_FUNCTION_SUPPORT_PORTC)
2744 case MHL_CBUS_SELECT_PORTC:
2745 if(GET_MHL_PATH_SUPPORT_PORTC())
2746 {
2747 if(bFlag)
2748 {
2749 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
2750 }
2751 else
2752 {
2753 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
2754 }
2755 }
2756
2757 break;
2758 #endif
2759
2760 #if(MHL_FUNCTION_SUPPORT_PORTD)
2761 case MHL_CBUS_SELECT_PORTD:
2762 if(GET_MHL_PATH_SUPPORT_PORTD())
2763 {
2764 if(bFlag)
2765 {
2766 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
2767 }
2768 else
2769 {
2770 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
2771 }
2772 }
2773
2774 break;
2775 #endif
2776
2777 default:
2778
2779 break;
2780 };
2781 }
2782
2783 //**************************************************************************
2784 // [Function Name]:
2785 // mhal_mhl_VbusCharge()
2786 // [Description]
2787 // MHL Vbus charge
2788 // [Arguments]:
2789 //
2790 // [Return]:
2791 //
2792 //**************************************************************************
mhal_mhl_VbusCharge(MS_U8 ucCbusSelect,MS_U8 bState)2793 void mhal_mhl_VbusCharge(MS_U8 ucCbusSelect, MS_U8 bState)
2794 {
2795 switch(ucCbusSelect)
2796 {
2797 #if(MHL_FUNCTION_SUPPORT_PORTA)
2798 case MHL_CBUS_SELECT_PORTA:
2799 if(GET_MHL_PATH_SUPPORT_PORTA())
2800 {
2801 if(bState == VBUS_SW_CHARGE)
2802 {
2803 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2804 }
2805 else if(bState == VBUS_SW_UNCHARGE)
2806 {
2807 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2808 }
2809 else
2810 {
2811 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2812 }
2813 }
2814
2815 break;
2816 #endif
2817
2818 #if(MHL_FUNCTION_SUPPORT_PORTB)
2819 case MHL_CBUS_SELECT_PORTB:
2820 if(GET_MHL_PATH_SUPPORT_PORTB())
2821 {
2822
2823 }
2824
2825 break;
2826 #endif
2827
2828 #if(MHL_FUNCTION_SUPPORT_PORTC)
2829 case MHL_CBUS_SELECT_PORTC:
2830 if(GET_MHL_PATH_SUPPORT_PORTC())
2831 {
2832 if(bState == VBUS_SW_CHARGE)
2833 {
2834 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2835 }
2836 else if(bState == VBUS_SW_UNCHARGE)
2837 {
2838 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2839 }
2840 else
2841 {
2842 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2843 }
2844 }
2845
2846 break;
2847 #endif
2848
2849 #if(MHL_FUNCTION_SUPPORT_PORTD)
2850 case MHL_CBUS_SELECT_PORTD:
2851 if(GET_MHL_PATH_SUPPORT_PORTD())
2852 {
2853 if(bState == VBUS_SW_CHARGE)
2854 {
2855 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2856 }
2857 else if(bState == VBUS_SW_UNCHARGE)
2858 {
2859 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2860 }
2861 else
2862 {
2863 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2864 }
2865 }
2866
2867 break;
2868 #endif
2869
2870 default:
2871
2872 break;
2873 };
2874 }
2875
2876 //**************************************************************************
2877 // [Function Name]:
2878 // mhal_mhl_CbusFloating()
2879 // [Description]
2880 // MHL cable floating
2881 // [Arguments]:
2882 //
2883 // [Return]:
2884 //
2885 //**************************************************************************
mhal_mhl_CbusFloating(MS_BOOL bFlag)2886 void mhal_mhl_CbusFloating(MS_BOOL bFlag)
2887 {
2888 if(bFlag)
2889 {
2890 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5));
2891 }
2892 else
2893 {
2894 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5));
2895 }
2896 }
2897
2898 //**************************************************************************
2899 // [Function Name]:
2900 // mhal_mhl_CbusStucktoLow()
2901 // [Description]
2902 //
2903 // [Arguments]:
2904 //
2905 // [Return]:
2906 //
2907 //**************************************************************************
mhal_mhl_CbusStucktoLow(MS_BOOL bFlag)2908 void mhal_mhl_CbusStucktoLow(MS_BOOL bFlag)
2909 {
2910 if(bFlag)
2911 {
2912 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask
2913 }
2914 else
2915 {
2916 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask
2917 }
2918
2919 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag
2920 }
2921
2922 //**************************************************************************
2923 // [Function Name]:
2924 // mhal_mhl_CbusWakeupInterrupt()
2925 // [Description]
2926 //
2927 // [Arguments]:
2928 //
2929 // [Return]:
2930 //
2931 //**************************************************************************
mhal_mhl_CbusWakeupInterrupt(MS_BOOL bFlag)2932 void mhal_mhl_CbusWakeupInterrupt(MS_BOOL bFlag)
2933 {
2934 if(bFlag)
2935 {
2936 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask
2937 }
2938 else
2939 {
2940 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask
2941 }
2942
2943 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag
2944 }
2945
2946 //**************************************************************************
2947 // [Function Name]:
2948 // mhal_mhl_SetVenderID()
2949 // [Description]
2950 //
2951 // [Arguments]:
2952 //
2953 // [Return]:
2954 //
2955 //**************************************************************************
mhal_mhl_SetVenderID(MS_U8 ucVenderID)2956 void mhal_mhl_SetVenderID(MS_U8 ucVenderID)
2957 {
2958 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8));
2959 }
2960
2961 //**************************************************************************
2962 // [Function Name]:
2963 // mhal_mhl_LoadEDID()
2964 // [Description]
2965 //
2966 // [Arguments]:
2967 //
2968 // [Return]:
2969 //
2970 //**************************************************************************
mhal_mhl_LoadEDID(MS_U8 * edid)2971 void mhal_mhl_LoadEDID(MS_U8 *edid)
2972 {
2973 MS_U16 ustemp = 0;
2974
2975 if(edid != NULL)
2976 {
2977 // Load EDID
2978 msg_mhl(printf("** Monet Load MHL EDID...\r\n"));
2979
2980 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable
2981
2982 for(ustemp = 0; ustemp <256; ustemp++)
2983 {
2984 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address
2985 W2BYTEMSK(REG_MHL_CBUS_53, edid[ustemp], 0x00FF); // data
2986 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger
2987 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0));
2988 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5));
2989 }
2990
2991 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable
2992 }
2993 }
2994
2995 //**************************************************************************
2996 // [Function Name]:
2997 // mhal_mhl_ReadEDID()
2998 // [Description]
2999 //
3000 // [Arguments]:
3001 //
3002 // [Return]:
3003 //
3004 //**************************************************************************
mhal_mhl_ReadEDID(MS_U16 usSize,MS_U8 * edid)3005 void mhal_mhl_ReadEDID(MS_U16 usSize, MS_U8 *edid)
3006 {
3007 MS_U16 ustemp = 0;
3008
3009 if(edid != NULL)
3010 {
3011 // Read EDID
3012 msg_mhl(printf("** Monet Read MHL EDID...\r\n"));
3013
3014 for(ustemp = 0; ustemp < usSize; ustemp++)
3015 {
3016 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address
3017 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger
3018 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0));
3019 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4));
3020
3021 edid[ustemp] = (MS_U8)((R2BYTE(REG_MHL_CBUS_53) & 0xFF00) >> 8); // data
3022 }
3023 }
3024 }
3025
3026 //**************************************************************************
3027 // [Function Name]:
3028 // mhal_mhl_LoadDeviceCapability()
3029 // [Description]
3030 //
3031 // [Arguments]:
3032 //
3033 // [Return]:
3034 //
3035 //**************************************************************************
mhal_mhl_LoadDeviceCapability(MS_U8 * devcap)3036 void mhal_mhl_LoadDeviceCapability(MS_U8 *devcap)
3037 {
3038 MS_U8 ucIndex = 0;
3039 MS_U8 uctemp = 0;
3040
3041 if(devcap != NULL)
3042 {
3043 msg_mhl(printf("** Monet Load DevCap...\r\n"));
3044
3045 // Load MHL device capability
3046 for(uctemp = 0; uctemp <8; uctemp++)
3047 {
3048 if(uctemp == 2)
3049 {
3050 ucIndex = 1;
3051 }
3052
3053 W2BYTE(REG_MHL_CBUS_01 +(uctemp *2), (devcap[(uctemp *2) +1 -ucIndex] <<8) | devcap[uctemp *2 -ucIndex]);
3054 }
3055
3056 W2BYTE(REG_MHL_CBUS_03, (devcap[3] <<8) | devcap[4]);
3057 W2BYTE(REG_MHL_CBUS_07, (devcap[11] <<8) | devcap[12]);
3058
3059 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0));
3060
3061 for(uctemp = 0; uctemp <2; uctemp++)
3062 {
3063 W2BYTE(REG_MHL_CBUS_19 +(uctemp *2), (devcap[(uctemp *2) +17] <<8) | devcap[(uctemp *2) +16]); // [15:0], MHL_ECBUS_SPEEDS
3064 }
3065 }
3066 }
3067
3068 //**************************************************************************
3069 // [Function Name]:
3070 // mhal_mhl_initial()
3071 // [Description]
3072 // MHL init
3073 // [Arguments]:
3074 // *edid: MHL EDID data
3075 // *devcap: MHL device capability
3076 // [Return]:
3077 //
3078 //**************************************************************************
mhal_mhl_initial(MS_U8 * edid,MS_U8 * devcap,MS_U8 ucVenderID)3079 MS_U8 mhal_mhl_initial(MS_U8 *edid, MS_U8 *devcap, MS_U8 ucVenderID)
3080 {
3081 MS_U16 uctemp = 0;
3082
3083 // Initial setting
3084 for(uctemp = 0; uctemp <(sizeof(tMHL_INITIAL_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3085 {
3086 W2BYTEMSK(tMHL_INITIAL_TABLE[uctemp].addr, tMHL_INITIAL_TABLE[uctemp].databuf, tMHL_INITIAL_TABLE[uctemp].mask);
3087 }
3088
3089 // ECbus initial setting
3090 _mhal_mhl_ECbusInitialSetting();
3091
3092 W2BYTEMSK(REG_PM_SLEEP_72_L, BMASK(7:6), BMASK(8:6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en_sel , [6]: reg_mhl_cable_detect_sel
3093
3094 _mhal_mhl_CbusAndClockSelect();
3095
3096 #if(MHL_INTERRUPT_USE_PM_IRQ)
3097 // Open PM irq mask
3098 W2BYTEMSK(0x2B28, 0, BIT(11));
3099 #endif
3100
3101 // Load EDID
3102 mhal_mhl_LoadEDID(edid);
3103
3104 // Load vendor ID
3105 mhal_mhl_SetVenderID(ucVenderID);
3106
3107 // Load DevCap
3108 mhal_mhl_LoadDeviceCapability(devcap);
3109
3110 // Clear Cbus received interrupt status
3111 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask
3112
3113 mhal_mhl_CbusStucktoLow(FALSE);
3114 mhal_mhl_CbusWakeupInterrupt(FALSE);
3115
3116 _mhal_mhl_MHLForceToAttach();
3117
3118 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
3119 {
3120 _mhal_mhl_RtermHWControl(uctemp, FALSE);
3121 }
3122
3123 _mhal_mhl_ForcePullDown100K(TRUE);
3124
3125 mhal_mhl_CbusFloating(TRUE);
3126
3127 return MHL_CHIP_FUNCTION_CAPABILITY;
3128 }
3129
3130 //**************************************************************************
3131 // [Function Name]:
3132 // mhal_mhl_InvertCableDetect()
3133 // [Description]
3134 //
3135 // [Arguments]:
3136 //
3137 // [Return]:
3138 //
3139 //**************************************************************************
mhal_mhl_InvertCableDetect(MS_U8 ucCbusSelect,MS_BOOL bCableDetectInvert)3140 void mhal_mhl_InvertCableDetect(MS_U8 ucCbusSelect, MS_BOOL bCableDetectInvert)
3141 {
3142 switch(ucCbusSelect)
3143 {
3144 #if(MHL_FUNCTION_SUPPORT_PORTA)
3145 case MHL_CBUS_SELECT_PORTA:
3146 if(GET_MHL_PATH_SUPPORT_PORTA())
3147 {
3148 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
3149 }
3150
3151 break;
3152 #endif
3153
3154 #if(MHL_FUNCTION_SUPPORT_PORTB)
3155 case MHL_CBUS_SELECT_PORTB:
3156 if(GET_MHL_PATH_SUPPORT_PORTB())
3157 {
3158
3159 }
3160
3161 break;
3162 #endif
3163
3164 #if(MHL_FUNCTION_SUPPORT_PORTC)
3165 case MHL_CBUS_SELECT_PORTC:
3166 if(GET_MHL_PATH_SUPPORT_PORTC())
3167 {
3168 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
3169 }
3170
3171 break;
3172 #endif
3173
3174 #if(MHL_FUNCTION_SUPPORT_PORTD)
3175 case MHL_CBUS_SELECT_PORTD:
3176 if(GET_MHL_PATH_SUPPORT_PORTD())
3177 {
3178 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
3179 }
3180
3181 break;
3182 #endif
3183
3184 default:
3185
3186 break;
3187 };
3188 }
3189
3190 //**************************************************************************
3191 // [Function Name]:
3192 // mhal_mhl_VbusConfigSetting()
3193 // [Description]
3194 //
3195 // [Arguments]:
3196 //
3197 // [Return]:
3198 //
3199 //**************************************************************************
mhal_mhl_VbusConfigSetting(MS_U8 ucCbusSelect,MS_U8 ucState)3200 void mhal_mhl_VbusConfigSetting(MS_U8 ucCbusSelect, MS_U8 ucState)
3201 {
3202 MS_U8 ucOutputState = ucState &(MHL_VBUS_LOW_ENABLE_MODE | MHL_VBUS_HIGH_ENABLE_MODE);
3203
3204 ucState = ucState &(MHL_VBUS_OUTPUT_MODE | MHL_VBUS_INVERSE_MODE);
3205
3206 switch(ucCbusSelect)
3207 {
3208 #if(MHL_FUNCTION_SUPPORT_PORTA)
3209 case MHL_CBUS_SELECT_PORTA:
3210 if(GET_MHL_PATH_SUPPORT_PORTA())
3211 {
3212 if(ucState == MHL_VBUS_OUTPUT_MODE)
3213 {
3214 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3215 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
3216 }
3217 else if(ucState > 0)
3218 {
3219 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3220 }
3221
3222 if(ucOutputState > 0)
3223 {
3224 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
3225 {
3226 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
3227 }
3228 else
3229 {
3230 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
3231 }
3232 }
3233 }
3234
3235 break;
3236 #endif
3237
3238 #if(MHL_FUNCTION_SUPPORT_PORTB)
3239 case MHL_CBUS_SELECT_PORTB:
3240 if(GET_MHL_PATH_SUPPORT_PORTB())
3241 {
3242
3243 }
3244
3245 break;
3246 #endif
3247
3248 #if(MHL_FUNCTION_SUPPORT_PORTC)
3249 case MHL_CBUS_SELECT_PORTC:
3250 if(GET_MHL_PATH_SUPPORT_PORTC())
3251 {
3252 if(ucState == MHL_VBUS_OUTPUT_MODE)
3253 {
3254 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3255 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
3256 }
3257 else if(ucState > 0)
3258 {
3259 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3260 }
3261
3262 if(ucOutputState > 0)
3263 {
3264 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
3265 {
3266 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
3267 }
3268 else
3269 {
3270 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
3271 }
3272 }
3273 }
3274
3275 break;
3276 #endif
3277
3278 #if(MHL_FUNCTION_SUPPORT_PORTD)
3279 case MHL_CBUS_SELECT_PORTD:
3280 if(GET_MHL_PATH_SUPPORT_PORTD())
3281 {
3282 if(ucState == MHL_VBUS_OUTPUT_MODE)
3283 {
3284 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3285 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
3286 }
3287 else if(ucState > 0)
3288 {
3289 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3290 }
3291
3292 if(ucOutputState > 0)
3293 {
3294 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
3295 {
3296 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
3297 }
3298 else
3299 {
3300 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
3301 }
3302 }
3303 }
3304
3305 break;
3306 #endif
3307
3308 default:
3309
3310 break;
3311 };
3312 }
3313
3314 //**************************************************************************
3315 // [Function Name]:
3316 // mhal_mhl_CableDetectPadSetting()
3317 // [Description]
3318 //
3319 // [Arguments]:
3320 //
3321 // [Return]:
3322 //
3323 //**************************************************************************
mhal_mhl_CableDetectPadSetting(MS_U8 ucSelect)3324 void mhal_mhl_CableDetectPadSetting(MS_U8 ucSelect)
3325 {
3326 // Nothing
3327 }
3328
3329 //**************************************************************************
3330 // [Function Name]:
3331 // mhal_mhl_CbusPadConfigSwitch()
3332 // [Description]
3333 //
3334 // [Arguments]:
3335 //
3336 // [Return]:
3337 //
3338 //**************************************************************************
mhal_mhl_CbusPadConfigSwitch(MS_U8 ucCbusSelect,MS_BOOL bFlag)3339 void mhal_mhl_CbusPadConfigSwitch(MS_U8 ucCbusSelect, MS_BOOL bFlag)
3340 {
3341 switch(ucCbusSelect)
3342 {
3343 #if(MHL_FUNCTION_SUPPORT_PORTA)
3344 case MHL_CBUS_SELECT_PORTA:
3345 if(GET_MHL_PATH_SUPPORT_PORTA())
3346 {
3347 if(bFlag)
3348 {
3349 _mhal_mhl_MHLForceToAttach();
3350 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3351 }
3352 else
3353 {
3354 _mhal_mhl_CbusForceToStandby();
3355 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
3356 }
3357 }
3358
3359 break;
3360 #endif
3361
3362 #if(MHL_FUNCTION_SUPPORT_PORTB)
3363 case MHL_CBUS_SELECT_PORTB:
3364 if(GET_MHL_PATH_SUPPORT_PORTB())
3365 {
3366
3367 }
3368
3369 break;
3370 #endif
3371
3372 #if(MHL_FUNCTION_SUPPORT_PORTC)
3373 case MHL_CBUS_SELECT_PORTC:
3374 if(GET_MHL_PATH_SUPPORT_PORTC())
3375 {
3376 if(bFlag)
3377 {
3378 _mhal_mhl_MHLForceToAttach();
3379 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3380 }
3381 else
3382 {
3383 _mhal_mhl_CbusForceToStandby();
3384 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
3385 }
3386 }
3387
3388 break;
3389 #endif
3390
3391 #if(MHL_FUNCTION_SUPPORT_PORTD)
3392 case MHL_CBUS_SELECT_PORTD:
3393 if(GET_MHL_PATH_SUPPORT_PORTD())
3394 {
3395 if(bFlag)
3396 {
3397 _mhal_mhl_MHLForceToAttach();
3398 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3399 }
3400 else
3401 {
3402 _mhal_mhl_CbusForceToStandby();
3403 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
3404 }
3405 }
3406
3407 break;
3408 #endif
3409
3410 default:
3411
3412 break;
3413 };
3414 }
3415
3416 //**************************************************************************
3417 // [Function Name]:
3418 // _mhal_mhl_CbusStatus()
3419 // [Description]:
3420 // MHL Cbus status
3421 // [Arguments]:
3422 //
3423 // [Return]:
3424 // Cbus status value
3425 //**************************************************************************
mhal_mhl_CbusStatus(void)3426 MS_U16 mhal_mhl_CbusStatus(void)
3427 {
3428 return (R2BYTE(REG_PM_MHL_CBUS_17));
3429 }
3430
3431 //**************************************************************************
3432 // [Function Name]:
3433 // mhal_mhl_CbusIsMscMsgReceived()
3434 // [Description]
3435 // MHL Cbus check whether msc message is received or not
3436 // [Arguments]:
3437 //
3438 // [Return]:
3439 // TRUE: recieved
3440 // FALSE: not yet
3441 //**************************************************************************
mhal_mhl_CbusIsMscMsgReceived(void)3442 MS_BOOL mhal_mhl_CbusIsMscMsgReceived(void)
3443 {
3444 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE);
3445
3446 if(bindex)
3447 {
3448 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0));
3449 }
3450
3451 return bindex;
3452 }
3453
3454 //**************************************************************************
3455 // [Function Name]:
3456 // mhal_mhl_CbusStucktoLowFlag()
3457 // [Description]
3458 //
3459 // [Arguments]:
3460 //
3461 // [Return]:
3462 //
3463 //**************************************************************************
mhal_mhl_CbusStucktoLowFlag(void)3464 MS_BOOL mhal_mhl_CbusStucktoLowFlag(void)
3465 {
3466 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(3)) ?TRUE: FALSE);
3467
3468 if(bindex)
3469 {
3470 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0));
3471 }
3472
3473 return bindex;
3474 }
3475
3476 //**************************************************************************
3477 // [Function Name]:
3478 // mhal_mhl_CbusWakeupIntFlag()
3479 // [Description]
3480 //
3481 // [Arguments]:
3482 //
3483 // [Return]:
3484 //
3485 //**************************************************************************
mhal_mhl_CbusWakeupIntFlag(void)3486 MS_BOOL mhal_mhl_CbusWakeupIntFlag(void)
3487 {
3488 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(7)) ?TRUE: FALSE);
3489
3490 if(bindex)
3491 {
3492 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4));
3493 }
3494
3495 return bindex;
3496 }
3497
3498 //**************************************************************************
3499 // [Function Name]:
3500 // mhal_mhl_GetECbusStateChangeFlag()
3501 // [Description]
3502 //
3503 // [Arguments]:
3504 //
3505 // [Return]:
3506 //
3507 //**************************************************************************
mhal_mhl_GetECbusStateChangeFlag(void)3508 MS_BOOL mhal_mhl_GetECbusStateChangeFlag(void)
3509 {
3510 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(0)) ?TRUE: FALSE);
3511
3512 if(bindex)
3513 {
3514 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0));
3515
3516 _mhal_mhl_ECbusStateChangeProc();
3517 }
3518
3519 return bindex;
3520 }
3521
3522 //**************************************************************************
3523 // [Function Name]:
3524 // mhal_mhl_GetEMSCReceiveFlag()
3525 // [Description]
3526 //
3527 // [Arguments]:
3528 //
3529 // [Return]:
3530 //
3531 //**************************************************************************
mhal_mhl_GetEMSCReceiveFlag(void)3532 MS_BOOL mhal_mhl_GetEMSCReceiveFlag(void)
3533 {
3534 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(12)) ?TRUE: FALSE);
3535
3536 if(bindex)
3537 {
3538 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12));
3539 }
3540
3541 return bindex;
3542 }
3543
3544 //**************************************************************************
3545 // [Function Name]:
3546 // mhal_mhl_GetEMSCSendStatus()
3547 // [Description]
3548 //
3549 // [Arguments]:
3550 //
3551 // [Return]:
3552 //
3553 //**************************************************************************
mhal_mhl_GetEMSCSendStatus(void)3554 MS_U8 mhal_mhl_GetEMSCSendStatus(void)
3555 {
3556 MS_U8 ucSendStatus = MHL_EMSC_SEND_NONE;
3557
3558 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(10)) // eMSC send pass interrupt.
3559 {
3560 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear
3561
3562 ucSendStatus = MHL_EMSC_SEND_PASS;
3563 }
3564 else if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(9)) // eMSC send fail interrupt.
3565 {
3566 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear
3567
3568 ucSendStatus = MHL_EMSC_SEND_FAIL;
3569 }
3570
3571 return ucSendStatus;
3572 }
3573
3574 //**************************************************************************
3575 // [Function Name]:
3576 // mhal_mhl_CBusWrite()
3577 // [Description]
3578 // MHL Cbus write trigger
3579 // [Arguments]:
3580 // *pdatabuf: Cbus tx data
3581 // [Return]:
3582 //
3583 //**************************************************************************
mhal_mhl_CBusWrite(mhalCbusFifo_S * pdatabuf)3584 MS_BOOL mhal_mhl_CBusWrite(mhalCbusFifo_S *pdatabuf)
3585 {
3586 MS_U8 uctemp = 0;
3587
3588 if(_mhal_mhl_IsCbusBusy())
3589 {
3590 return FALSE;
3591 }
3592
3593 for(uctemp = 0; uctemp < pdatabuf->lens; uctemp++)
3594 {
3595 W2BYTE(REG_MHL_CBUS_26 +uctemp *2, pdatabuf->databuf[uctemp]);
3596 }
3597
3598 // clear the unsed parts
3599 W2BYTE(REG_MHL_CBUS_26 +((pdatabuf->lens) *2), 0);
3600
3601 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send
3602
3603 #if(MHL_DEBUG_SEND_MSC)
3604 for(uctemp = 0; uctemp < pdatabuf->lens; uctemp++)
3605 {
3606 if((pdatabuf->databuf[uctemp]) &BIT(8))
3607 {
3608 msg_mhl(printf(" MHL send MSG command = %x\r\n", (pdatabuf->databuf[uctemp] &BMASK(7:0))));
3609 }
3610 else
3611 {
3612 msg_mhl(printf(" MHL send MSG data = %x\r\n", (pdatabuf->databuf[uctemp] &BMASK(7:0))));
3613 }
3614 }
3615
3616 #endif
3617
3618 return TRUE;
3619 }
3620
3621 //**************************************************************************
3622 // [Function Name]:
3623 // _mhal_mhl_Cbus_SetPathEn()
3624 // [Description]:
3625 // MHL Cbus set path enable
3626 // [Arguments]:
3627 // TRUE: Enable
3628 // FALSE: Disable
3629 // [Return]:
3630 //
3631 //**************************************************************************
mhal_mhl_Cbus_SetPathEn(MS_BOOL bflag)3632 void mhal_mhl_Cbus_SetPathEn(MS_BOOL bflag)
3633 {
3634 if(bflag) // set state to PATH_EN
3635 {
3636 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12));
3637 }
3638 else // clear state to not PATH_EN
3639 {
3640 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13));
3641 }
3642 }
3643
3644 //**************************************************************************
3645 // [Function Name]:
3646 // mhal_mhl_CbusIntCB()
3647 // [Description]
3648 // MHL Cbus Interrupt Call Back function
3649 // [Arguments]:
3650 // *rcstate: recevied state, 0:normal / 1:timeout
3651 // *rccmd: recevied command
3652 // *rcdata: recevied data
3653 // *rclen: received length
3654 // *bIsCmdInData: Is command in data field
3655 // [Return]:
3656 //
3657 //**************************************************************************
mhal_mhl_CbusIntCB(MS_U8 * rcstate,MS_U8 * rccmd,MS_U8 * rcdata,MS_U8 * rclen,MS_U8 * bIsCmdInData)3658 MS_BOOL mhal_mhl_CbusIntCB(MS_U8 *rcstate, MS_U8 *rccmd, MS_U8 *rcdata, MS_U8 *rclen, MS_U8 *bIsCmdInData)
3659 {
3660 MS_BOOL bindex = FALSE;
3661 MS_U8 uctemp = 0;
3662 MS_U16 reg_val;
3663
3664 *rcstate = R2BYTE(REG_MHL_CBUS_3B) & 0x000F; // received state, 0: normal, 1: timeout
3665
3666 //W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); // clear INT
3667
3668 reg_val = R2BYTE(REG_MHL_CBUS_3C);
3669
3670 if(!(reg_val &BIT(8))) // Received data
3671 {
3672 bindex = TRUE;
3673 }
3674
3675 *rccmd = reg_val & 0x00FF;
3676 *bIsCmdInData = FALSE;
3677
3678 for(uctemp = 0; uctemp <=(MHL_CBUS_DATA_SIZE +1); uctemp++) // offset+16bytes+EOF
3679 {
3680 reg_val = R2BYTE(REG_MHL_CBUS_3D +(uctemp *2));
3681
3682 if(reg_val & BIT(15))
3683 {
3684 rcdata[uctemp] = reg_val & 0x00FF;
3685
3686 if(((uctemp <= 2) ||(uctemp == (MHL_CBUS_DATA_SIZE +1))) && !(*bIsCmdInData))
3687 {
3688 *bIsCmdInData = (reg_val & BIT(8)) ? TRUE : FALSE;
3689 }
3690 }
3691 else
3692 {
3693 *rclen = uctemp;
3694 break;
3695 }
3696 }
3697
3698 // CTS 6.3.11.19
3699 if(uctemp >(MHL_CBUS_DATA_SIZE +1))
3700 {
3701 *rclen = MHL_CBUS_DATA_SIZE +2;
3702 }
3703
3704 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO
3705
3706 return bindex;
3707 }
3708
3709 //**************************************************************************
3710 // [Function Name]:
3711 // mdrv_mhl_CBusCheckBCHError()
3712 // [Description]:
3713 // MHL Cbus check BCH error
3714 // [Arguments]:
3715 //
3716 // [Return]:
3717 //
3718 //**************************************************************************
mhal_mhl_CBusCheckBCHError(void)3719 MS_BOOL mhal_mhl_CBusCheckBCHError(void)
3720 {
3721 MS_BOOL bindex = FALSE;
3722
3723 return bindex;
3724 }
3725
3726 //**************************************************************************
3727 // [Function Name]:
3728 // mhal_mhl_CablePlugProc()
3729 // [Description]
3730 //
3731 // [Arguments]:
3732 //
3733 // [Return]:
3734 //
3735 //**************************************************************************
mhal_mhl_CablePlugProc(MS_U8 ucCbusSelect)3736 void mhal_mhl_CablePlugProc(MS_U8 ucCbusSelect)
3737 {
3738 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
3739
3740 #if(DMHL_LG_PRADA_PATCH)
3741 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
3742 #endif
3743
3744 _mhal_mhl_Mhl24bitsModeSetting(ucCbusSelect);
3745
3746 if(mhal_mhl_CheckInputPort(ucCbusSelect))
3747 {
3748 _mhal_mhl_AudioPathSelect(TRUE);
3749 }
3750
3751 _mhal_mhl_ForcePullDown100K(FALSE);
3752 }
3753
3754 //**************************************************************************
3755 // [Function Name]:
3756 // mhal_mhl_CableRemoveProc()
3757 // [Description]
3758 //
3759 // [Arguments]:
3760 //
3761 // [Return]:
3762 //
3763 //**************************************************************************
mhal_mhl_CableRemoveProc(MS_U8 ucCbusSelect)3764 void mhal_mhl_CableRemoveProc(MS_U8 ucCbusSelect)
3765 {
3766 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_HDMI_RTERM);
3767
3768 _mhal_mhl_HdmiBypassModeSetting(ucCbusSelect);
3769
3770 // Disable ECbus state change IRQ
3771 _mhal_mhl_SetECbusStateChangeInterrupt(FALSE);
3772 // Disable eMSC receive IRQ
3773 _mhal_mhl_SetEMSCReceiveInterrupt(FALSE);
3774
3775 if(mhal_mhl_CheckInputPort(ucCbusSelect))
3776 {
3777 _mhal_mhl_AudioPathSelect(FALSE);
3778 }
3779
3780 _mhal_mhl_ForcePullDown100K(TRUE);
3781
3782 _mhal_mhl_Version3PhyEnable(ucCbusSelect, FALSE);
3783 // Disable ECbus
3784 _mhal_mhl_ECbusEnableSetting(FALSE);
3785 // Set short read address to 0x08
3786 _mhal_mhl_SetShortReadAddress(FALSE);
3787 }
3788
3789 //**************************************************************************
3790 // [Function Name]:
3791 // mhal_mhl_CbusConnectProc()
3792 // [Description]
3793 //
3794 // [Arguments]:
3795 //
3796 // [Return]:
3797 //
3798 //**************************************************************************
mhal_mhl_CbusConnectProc(MS_U8 ucCbusSelect)3799 void mhal_mhl_CbusConnectProc(MS_U8 ucCbusSelect)
3800 {
3801 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_MHL_RTERM);
3802
3803 #if(DMHL_LG_PRADA_PATCH)
3804 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, FALSE);
3805 #endif
3806
3807 mhal_mhl_CbusStucktoLow(TRUE);
3808 }
3809
3810 //**************************************************************************
3811 // [Function Name]:
3812 // mhal_mhl_CbusStucktoLowProc()
3813 // [Description]
3814 //
3815 // [Arguments]:
3816 //
3817 // [Return]:
3818 //
3819 //**************************************************************************
mhal_mhl_CbusStucktoLowProc(MS_U8 ucCbusSelect)3820 void mhal_mhl_CbusStucktoLowProc(MS_U8 ucCbusSelect)
3821 {
3822 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
3823
3824 #if(DMHL_LG_PRADA_PATCH)
3825 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
3826 #endif
3827
3828 mhal_mhl_CDRModeMonitor(ucCbusSelect, FALSE);
3829 // Set short read address to 0x08
3830 _mhal_mhl_SetShortReadAddress(FALSE);
3831 }
3832
3833 //**************************************************************************
3834 // [Function Name]:
3835 // mhal_mhl_SourceChangeProc()
3836 // [Description]
3837 //
3838 // [Arguments]:
3839 //
3840 // [Return]:
3841 //
3842 //**************************************************************************
mhal_mhl_SourceChangeProc(MS_U8 ucCbusSelect)3843 void mhal_mhl_SourceChangeProc(MS_U8 ucCbusSelect)
3844 {
3845 MS_BOOL bLinkRate6GFlag = FALSE;
3846
3847 if(ucMHL3LinkRate == MHL_AV_LINK_600)
3848 {
3849 bLinkRate6GFlag = TRUE;
3850 }
3851
3852 if(mhal_mhl_CheckInputPort(ucCbusSelect))
3853 {
3854 _mhal_mhl_AudioPathSelect(TRUE);
3855 }
3856 else
3857 {
3858 _mhal_mhl_AudioPathSelect(FALSE);
3859 }
3860 }
3861
3862 //**************************************************************************
3863 // [Function Name]:
3864 // mhal_mhl_ClockModeSwitchProc()
3865 // [Description]
3866 //
3867 // [Arguments]:
3868 //
3869 // [Return]:
3870 //
3871 //**************************************************************************
mhal_mhl_ClockModeSwitchProc(MS_U8 ucCbusSelect,MS_BOOL bPPmode)3872 void mhal_mhl_ClockModeSwitchProc(MS_U8 ucCbusSelect, MS_BOOL bPPmode)
3873 {
3874 if(bPPmode)
3875 {
3876 _mhal_mhl_MhlPackedPixelModeSetting(ucCbusSelect);
3877 }
3878 else
3879 {
3880 _mhal_mhl_Mhl24bitsModeSetting(ucCbusSelect);
3881 }
3882 }
3883
3884 //**************************************************************************
3885 // [Function Name]:
3886 // mhal_mhl_CbusWakeupIntSetting()
3887 // [Description]
3888 //
3889 // [Arguments]:
3890 //
3891 // [Return]:
3892 //
3893 //**************************************************************************
mhal_mhl_CbusWakeupIntSetting(MS_U8 ucCbusSelect,MS_BOOL bFlag)3894 void mhal_mhl_CbusWakeupIntSetting(MS_U8 ucCbusSelect, MS_BOOL bFlag)
3895 {
3896 if(bFlag)
3897 {
3898 _mhal_mhl_CbusForceToStandby();
3899 mhal_mhl_CbusWakeupInterrupt(TRUE);
3900 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_CHARGE);
3901 }
3902 else
3903 {
3904 _mhal_mhl_MHLForceToAttach();
3905 mhal_mhl_CbusWakeupInterrupt(FALSE);
3906 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3907 }
3908 }
3909
3910 //**************************************************************************
3911 // [Function Name]:
3912 // mhal_mhl_RtermControlHWMode()
3913 // [Description]
3914 //
3915 // [Arguments]:
3916 //
3917 // [Return]:
3918 //
3919 //**************************************************************************
mhal_mhl_RtermControlHWMode(MS_U8 ucCbusSelect,MS_BOOL bFlag)3920 void mhal_mhl_RtermControlHWMode(MS_U8 ucCbusSelect, MS_BOOL bFlag)
3921 {
3922 MS_U16 ustemp = mhal_mhl_CbusStatus();
3923
3924 if(!bFlag) // HW to SW control rterm
3925 {
3926 if((ustemp & BMASK(1:0)) == 0x03)
3927 {
3928 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_MHL_RTERM);
3929 }
3930 else
3931 {
3932 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
3933 }
3934 }
3935
3936 _mhal_mhl_RtermHWControl(ucCbusSelect, bFlag);
3937 }
3938
3939 //**************************************************************************
3940 // [Function Name]:
3941 // mhal_mhl_AdjustSettingIControl()
3942 // [Description]
3943 //
3944 // [Arguments]:
3945 //
3946 // [Return]:
3947 //
3948 //**************************************************************************
mhal_mhl_AdjustSettingIControl(MS_U8 ucIControl)3949 void mhal_mhl_AdjustSettingIControl(MS_U8 ucIControl)
3950 {
3951 ucIControlValue = ucIControl;
3952 }
3953
3954 //**************************************************************************
3955 // [Function Name]:
3956 // mhal_mhl_AdjustImpedanceSetting()
3957 // [Description]
3958 //
3959 // [Arguments]:
3960 //
3961 // [Return]:
3962 //
3963 //**************************************************************************
mhal_mhl_AdjustImpedanceSetting(MS_U8 ucImpedance)3964 void mhal_mhl_AdjustImpedanceSetting(MS_U8 ucImpedance)
3965 {
3966 ucImpedanceValue = ucImpedance;
3967 }
3968
3969 //**************************************************************************
3970 // [Function Name]:
3971 // mhal_mhl_GetSignalStableFlag()
3972 // [Description]
3973 //
3974 // [Arguments]:
3975 //
3976 // [Return]:
3977 //
3978 //**************************************************************************
mhal_mhl_GetSignalStableFlag(void)3979 MS_BOOL mhal_mhl_GetSignalStableFlag(void)
3980 {
3981 return bMHLSignalStable;
3982 }
3983
3984 //**************************************************************************
3985 // [Function Name]:
3986 // mhal_mhl_PowerControl()
3987 // [Description]
3988 // MHL power control
3989 // [Arguments]:
3990 //
3991 // [Return]:
3992 //
3993 //**************************************************************************
mhal_mhl_LoadPowerOnTbl(void)3994 void mhal_mhl_LoadPowerOnTbl(void)
3995 {
3996 MS_U8 uctemp = 0;
3997
3998 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_ON_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3999 {
4000 W2BYTEMSK(tMHL_POWER_ON_TABLE[uctemp].addr, tMHL_POWER_ON_TABLE[uctemp].databuf, tMHL_POWER_ON_TABLE[uctemp].mask);
4001 }
4002
4003 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
4004 {
4005 _mhal_mhl_RxRtermControl(uctemp, RX_HDMI_RTERM);
4006 }
4007 }
4008
mhal_mhl_LoadPowerStandbyTbl(void)4009 void mhal_mhl_LoadPowerStandbyTbl(void)
4010 {
4011 MS_U8 uctemp = 0;
4012
4013 //_mhal_mhl_CbusForceToStandby();
4014
4015 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_SAVING_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
4016 {
4017 W2BYTEMSK(tMHL_POWER_SAVING_TABLE[uctemp].addr, tMHL_POWER_SAVING_TABLE[uctemp].databuf, tMHL_POWER_SAVING_TABLE[uctemp].mask);
4018 }
4019
4020 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
4021 {
4022 _mhal_mhl_RxRtermControl(uctemp, RX_RTERM_OFF);
4023 mhal_mhl_VbusCharge(uctemp, VBUS_SW_CHARGE);
4024 }
4025 }
4026
mhal_mhl_LoadPowerDownTbl(void)4027 void mhal_mhl_LoadPowerDownTbl(void)
4028 {
4029 MS_U8 uctemp = 0;
4030
4031 //_mhal_mhl_CbusForceToStandby();
4032
4033 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_DOWN_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
4034 {
4035 W2BYTEMSK(tMHL_POWER_DOWN_TABLE[uctemp].addr, tMHL_POWER_DOWN_TABLE[uctemp].databuf, tMHL_POWER_DOWN_TABLE[uctemp].mask);
4036 }
4037
4038 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
4039 {
4040 _mhal_mhl_RxRtermControl(uctemp, RX_RTERM_OFF);
4041 }
4042 }
4043
4044 //**************************************************************************
4045 // [Function Name]:
4046 // mhal_mhl_SetHPD()
4047 // [Description]
4048 // config HPD in combo(MHL/HDMI) port A
4049 // [Arguments]:
4050 //
4051 // [Return]:
4052 //
4053 //**************************************************************************
mhal_mhl_SetHPD(MS_BOOL bflag)4054 void mhal_mhl_SetHPD(MS_BOOL bflag)
4055 {
4056 if(bflag) // HPD is high
4057 {
4058 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen
4059 //msg_mhl(printf("**MHL_HPD is High"));
4060 }
4061 else // hpd is low
4062 {
4063 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen
4064 //msg_mhl(printf("**MHL_HPD is Low"));
4065 }
4066 }
4067
4068 //**************************************************************************
4069 // [Function Name]:
4070 // mhal_mhl_GetDDCErrorCode()
4071 // [Description]
4072 // Get DDC error code
4073 // [Arguments]:
4074 //
4075 // [Return]:
4076 //
4077 //**************************************************************************
mhal_mhl_GetDDCErrorCode(void)4078 MS_U8 mhal_mhl_GetDDCErrorCode(void)
4079 {
4080 return (R2BYTE(REG_MHL_CBUS_21)>>8);
4081 }
4082
4083 #if(MHL_CBUS_OPERATION_MODE == MHL_CBUS_HW_REPLY_MODE)
4084 //**************************************************************************
4085 // [Function Name]:
4086 // mhal_mhl_CheckSRAMReceiveBuffer()
4087 // [Description]
4088 //
4089 // [Arguments]:
4090 //
4091 // [Return]:
4092 //
4093 //**************************************************************************
mhal_mhl_CheckSRAMReceiveBuffer(void)4094 MS_BOOL mhal_mhl_CheckSRAMReceiveBuffer(void)
4095 {
4096 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE);
4097 }
4098
4099 //**************************************************************************
4100 // [Function Name]:
4101 // mhal_mhl_GetSRAMReceiveData()
4102 // [Description]
4103 //
4104 // [Arguments]:
4105 //
4106 // [Return]:
4107 //
4108 //**************************************************************************
mhal_mhl_GetSRAMReceiveData(void)4109 MS_U16 mhal_mhl_GetSRAMReceiveData(void)
4110 {
4111 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15));
4112
4113 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14));
4114
4115 return R2BYTE(REG_MHL_CBUS_0F);
4116 }
4117
4118 #endif
4119
4120 #if(DMHL_TEST_SIGNAL_SUPPORT)
4121 //**************************************************************************
4122 // [Function Name]:
4123 // mhal_mhl_AdjustCommonModeResistor()
4124 // [Description]:
4125 //
4126 // [Arguments]:
4127 //
4128 // [Return]:
4129 //
4130 //**************************************************************************
mhal_mhl_TestSignal(MS_BOOL bflag)4131 void mhal_mhl_TestSignal(MS_BOOL bflag)
4132 {
4133 if(bflag)
4134 {
4135 W2BYTEMSK(0x001106, BIT(10), BIT(10));
4136 }
4137 else
4138 {
4139 W2BYTEMSK(0x001106, 0, BIT(10));
4140 }
4141 }
4142
4143 #endif
4144
4145 //**************************************************************************
4146 // [Function Name]:
4147 // mhal_mhl_SetMainLinkRate()
4148 // [Description]
4149 //
4150 // [Arguments]:
4151 //
4152 // [Return]:
4153 //
4154 //**************************************************************************
mhal_mhl_SetMainLinkRate(MS_U8 ucCbusSelect,MS_U8 ucLinkRate)4155 void mhal_mhl_SetMainLinkRate(MS_U8 ucCbusSelect, MS_U8 ucLinkRate)
4156 {
4157 MS_BOOL bLinkRate6GFlag = FALSE;
4158
4159 _mhal_mhl_Version3PhyEnable(ucCbusSelect, TRUE);
4160
4161 switch(ucCbusSelect)
4162 {
4163 #if(MHL_FUNCTION_SUPPORT_PORTA)
4164 case MHL_CBUS_SELECT_PORTA:
4165 if(GET_MHL_PATH_SUPPORT_PORTA())
4166 {
4167 if(ucLinkRate == MHL_AV_LINK_600)
4168 {
4169 bLinkRate6GFlag = TRUE;
4170 }
4171 else // MHL_AV_LINK_150 or MHL_AV_LINK_300
4172 {
4173
4174 }
4175
4176 W2BYTEMSK(REG_COMBO_PHY1_P0_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data rate
4177 }
4178
4179 break;
4180 #endif
4181
4182 #if(MHL_FUNCTION_SUPPORT_PORTB)
4183 case MHL_CBUS_SELECT_PORTB:
4184 if(GET_MHL_PATH_SUPPORT_PORTB())
4185 {
4186 if(ucLinkRate == MHL_AV_LINK_600)
4187 {
4188 bLinkRate6GFlag = TRUE;
4189 }
4190 else // MHL_AV_LINK_150 or MHL_AV_LINK_300
4191 {
4192
4193 }
4194
4195 W2BYTEMSK(REG_COMBO_PHY1_P1_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data rate
4196 }
4197
4198 break;
4199 #endif
4200
4201 #if(MHL_FUNCTION_SUPPORT_PORTC)
4202 case MHL_CBUS_SELECT_PORTC:
4203 if(GET_MHL_PATH_SUPPORT_PORTC())
4204 {
4205 if(ucLinkRate == MHL_AV_LINK_600)
4206 {
4207 bLinkRate6GFlag = TRUE;
4208 }
4209 else // MHL_AV_LINK_150 or MHL_AV_LINK_300
4210 {
4211
4212 }
4213
4214 W2BYTEMSK(REG_COMBO_PHY1_P2_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data rate
4215 }
4216
4217 break;
4218 #endif
4219
4220 #if(MHL_FUNCTION_SUPPORT_PORTD)
4221 case MHL_CBUS_SELECT_PORTD:
4222 if(GET_MHL_PATH_SUPPORT_PORTD())
4223 {
4224 if(ucLinkRate == MHL_AV_LINK_600)
4225 {
4226 bLinkRate6GFlag = TRUE;
4227 }
4228 else // MHL_AV_LINK_150 or MHL_AV_LINK_300
4229 {
4230
4231 }
4232
4233 W2BYTEMSK(REG_COMBO_PHY1_P3_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data rate
4234 }
4235
4236 break;
4237 #endif
4238
4239 default:
4240
4241 break;
4242 };
4243
4244 ucMHL3LinkRate = ucLinkRate;
4245 }
4246
4247 //**************************************************************************
4248 // [Function Name]:
4249 // mhal_mhl_GetECbusStatusFlag()
4250 // [Description]:
4251 //
4252 // [Arguments]:
4253 //
4254 // [Return]:
4255 //
4256 //**************************************************************************
mhal_mhl_GetECbusStatusFlag(void)4257 MS_U8 mhal_mhl_GetECbusStatusFlag(void)
4258 {
4259 MS_U8 ucTrainState = (R2BYTE(REG_MHL_ECBUS_PHY_69) >> 12);
4260 MS_U8 ucECbusStatusFlag = 0;
4261
4262 if((ucECbusTrainState < MHL_ECBUS_STATE_FAIL) && (ucECbusTrainState >= MHL_ECBUS_STATE_SOURCE_ACTIVE))
4263 {
4264 ucECbusStatusFlag |= MHL_ECBUS_STATUS_TRAINING_PASS;
4265 }
4266
4267 if(R2BYTE(REG_MHL_ECBUS_PHY_6F) &BIT(13)) // [13]: ECbus clock lock flag
4268 {
4269 ucECbusStatusFlag |= MHL_ECBUS_STATUS_CLOCK_LOCK;
4270 }
4271
4272 if((ucTrainState >= MHL_ECBUS_TRAIN_WAIT_RRCEIVE_COMMA2) && (ucTrainState <= MHL_ECBUS_TRAIN_DONE))//Whan state of REG_PM_MHL_CBUS2_56 is equla 3, than state of REG_PM_MHL_CBUS2_69[51:12] will from 1 to 7.
4273 {
4274 //W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0200, BMASK(15:0)); // for auto train
4275 #if(MHL_ECBUS_AUTO_TRAINING)
4276 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13));
4277 #endif
4278 }
4279
4280 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(7)) // REG_MHL_CBUS2_3A[7]
4281 {
4282 ucECbusStatusFlag |= MHL_ECBUS_STATUS_SLOT_SYNC_DONE;
4283 }
4284
4285 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(15)) // REG_MHL_CBUS2_3A[15]
4286 {
4287 ucECbusStatusFlag |= MHL_ECBUS_STATUS_EMSC_SYNC_DONE;
4288 }
4289
4290 if(ucECbusTrainFailCount > 10)
4291 {
4292 ucECbusStatusFlag |= MHL_ECBUS_STATUS_RETRY_TIMEOUT;
4293
4294 ucECbusTrainFailCount = 0;
4295 }
4296
4297 return ucECbusStatusFlag;
4298 }
4299
4300 //**************************************************************************
4301 // [Function Name]:
4302 // mhal_mhl_ECbusEventProc()
4303 // [Description]
4304 //
4305 // [Arguments]:
4306 //
4307 // [Return]:
4308 //
4309 //**************************************************************************
mhal_mhl_ECbusEventProc(MS_U8 ucCbusSelect,MS_U8 ucECbusEvent)4310 void mhal_mhl_ECbusEventProc(MS_U8 ucCbusSelect, MS_U8 ucECbusEvent)
4311 {
4312 static MS_U8 ucECbusState = MHL_ECBUS_STATE_DISABLE;
4313
4314 if(ucECbusTrainState != ucECbusState)
4315 {
4316 msg_mhl(printf("** MHL eCbus state %x\r\n", ucECbusTrainState));
4317
4318 ucECbusState = ucECbusTrainState;
4319 }
4320
4321 switch(ucECbusEvent)
4322 {
4323 case MHL_ECBUS_EVENT_PREPARE_MODE_UP:
4324 // Disable stuck to low interrupt
4325 mhal_mhl_CbusStucktoLow(FALSE);
4326 // Disable connect detect
4327 _mhal_mhl_CbusConnectCheckEnable(FALSE);
4328
4329 break;
4330
4331 case MHL_ECBUS_EVENT_MODE_UP_PROCESS:
4332 // Enable ECbus
4333 _mhal_mhl_ECbusEnableSetting(TRUE);
4334 // Set short read address to 0x70
4335 _mhal_mhl_SetShortReadAddress(TRUE);
4336 // Enable ECbus state change IRQ
4337 _mhal_mhl_SetECbusStateChangeInterrupt(TRUE);
4338 // Enable eMSC receive IRQ
4339 _mhal_mhl_SetEMSCReceiveInterrupt(TRUE);
4340
4341 _mhal_mhl_ECbusModeUpProc();
4342
4343 ucECbusTrainFailCount = 0;
4344
4345 break;
4346
4347 case MHL_ECBUS_EVENT_PREPARE_MODE_DOWN:
4348
4349 break;
4350
4351 case MHL_ECBUS_EVENT_MODE_DOWN_PROCESS:
4352 case MHL_ECBUS_EVENT_STUCK_TO_LOW:
4353 // Enable connect detect
4354 _mhal_mhl_CbusConnectCheckEnable(TRUE);
4355 // Disable ECbus
4356 _mhal_mhl_ECbusEnableSetting(FALSE);
4357 // Clear short read address to 0x08
4358 _mhal_mhl_SetShortReadAddress(FALSE);
4359 // Disable ECbus state change IRQ
4360 _mhal_mhl_SetECbusStateChangeInterrupt(FALSE);
4361 // Disable eMSC receive IRQ
4362 _mhal_mhl_SetEMSCReceiveInterrupt(FALSE);
4363 // Disable MHL3 phy
4364 _mhal_mhl_Version3PhyEnable(ucCbusSelect, FALSE);
4365 // Reset all status
4366 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF);
4367
4368 _mhal_mhl_CbusEngineReset();
4369
4370 break;
4371
4372 case MHL_ECBUS_EVENT_UNLOCK_RESET:
4373 //_mhal_mhl_ECbusDmuxEnable(FALSE);
4374 _mhal_mhl_ECbusStateReset();
4375
4376 ucECbusTrainFailCount = 0;
4377
4378 break;
4379
4380 #if(MHL_ECBUS_COMMAND_PARSING)
4381 case MHL_ECBUS_EVENT_ECBUS_COMMAND_PARSING:
4382 _mhal_mhl_GetECbusCommand();
4383
4384 break;
4385
4386 #endif
4387
4388 default:
4389
4390 break;
4391 };
4392 }
4393
4394 //**************************************************************************
4395 // [Function Name]:
4396 // mhal_mhl_GetEMSCReceiveData()
4397 // [Description]
4398 //
4399 // [Arguments]:
4400 //
4401 // [Return]:
4402 //
4403 //**************************************************************************
mhal_mhl_GetEMSCReceiveData(MS_U8 * bReveiceEMSC)4404 void mhal_mhl_GetEMSCReceiveData(MS_U8 *bReveiceEMSC)
4405 {
4406 MS_U8 uctemp = 0;
4407 MS_U16 usEMSCFreeBuffer = 0;
4408
4409 usEMSCFreeBuffer = (R2BYTE(REG_MHL_ECBUS_24) &BMASK(9:0)); // REG_MHL_ECBUS_24[9:0]
4410
4411 usEMSCFreeBuffer = MHL_EMSC_DATA_SIZE - usEMSCFreeBuffer;
4412
4413 bReveiceEMSC[0] = usEMSCFreeBuffer;
4414
4415 msg_mhl(printf("** MHL eMSC length %d\r\n", usEMSCFreeBuffer));
4416
4417 for(uctemp = 0; uctemp < usEMSCFreeBuffer; uctemp++)
4418 {
4419 bReveiceEMSC[uctemp +1] = _mhal_mhl_GetSRAMReceiveEMSCData();
4420
4421 if(uctemp == 1) // Check length remaining
4422 {
4423 usEMSCFreeBuffer = bReveiceEMSC[uctemp +1] +2;
4424 }
4425
4426 msg_mhl(printf("** MHL eMSC data %x\r\n", bReveiceEMSC[uctemp +1]));
4427 }
4428
4429 W2BYTEMSK(REG_MHL_ECBUS_1C, usEMSCFreeBuffer, BMASK(9:0));
4430 W2BYTEMSK(REG_MHL_ECBUS_1C, BIT(15), BIT(15));
4431 }
4432
4433 //**************************************************************************
4434 // [Function Name]:
4435 // mhal_mhl_InsertEMSCSendData()
4436 // [Description]
4437 //
4438 // [Arguments]:
4439 //
4440 // [Return]:
4441 //
4442 //**************************************************************************
mhal_mhl_InsertEMSCSendData(MS_U8 ucLength,MS_U8 * bSendEMSC)4443 void mhal_mhl_InsertEMSCSendData(MS_U8 ucLength, MS_U8 *bSendEMSC)
4444 {
4445 MS_U8 uctemp = 0;
4446 MS_U16 usPayloadCRC = 0xFFFF;
4447
4448 if((ucLength > 0) && (bSendEMSC != NULL))
4449 {
4450 W2BYTEMSK(REG_MHL_ECBUS_1B, (ucLength -1), BMASK(9:0)); // Request command byte count
4451 W2BYTEMSK(REG_MHL_ECBUS_79, _mhal_mhl_GetEMSCTwoByteCRC(0, (ucLength -1)) , BMASK(2:0)); // byte count CRC
4452
4453 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0
4454 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address
4455
4456 for(uctemp = 0; uctemp < ucLength; uctemp++)
4457 {
4458 _mhal_mhl_InsertSRAMSendEMSCData(bSendEMSC[uctemp]);
4459
4460 msg_mhl(printf("** MHL payload value %x\r\n", bSendEMSC[uctemp]));
4461
4462 usPayloadCRC = _mhal_mhl_GetEMSCPayloadCRC(bSendEMSC[uctemp], usPayloadCRC);
4463 }
4464
4465 W2BYTEMSK(REG_MHL_ECBUS_19, BIT(15), BIT(15)); // eMSC payload CRC ove
4466 W2BYTE(REG_MHL_ECBUS_1A, (usPayloadCRC ^0xFFFF)); // eMSC payload CRC value
4467
4468 msg_mhl(printf("** MHL payload CRC value %x\r\n", (usPayloadCRC ^0xFFFF)));
4469
4470 W2BYTEMSK(REG_MHL_ECBUS_1B, BIT(15), BIT(15)); // REG_MHL_ECBUS2_1B[15]
4471 }
4472 }
4473
4474 #endif // _MHAL_MHL_C_
4475
4476