Lines Matching refs:BIT
151 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
152 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
154 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
163 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
166 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
168 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
171 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
175 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
180 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
181 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
182 {REG_PM_MHL_CBUS_30, BIT(1), BIT(1)}, // [1]: cbus conflict_int mask
183 …{REG_PM_MHL_CBUS_38, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused …
184 {REG_MHL_CBUS_14, BIT(13), BIT(13)}, // [13]: int mask for monitor_sram_full
185 {REG_MHL_CBUS_18, BIT(13), BIT(13)}, // [13]: send rcv_pkt_ddc_sw_overwrite_err_in mask
186 …{REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1…
187 {REG_MHL_CBUS_1B, BIT(1), BIT(1)}, // [1]: receive ddc packet valid mask
188 …{REG_MHL_CBUS_1F, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: ddc access edid timeout int mask, [1]: cl…
189 {REG_MHL_CBUS_21, BIT(5), BIT(5)}, // [5]: ddc error interrupt mask
190 …{REG_MHL_CBUS_22, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: ddc access hdcp timeout int…
191 {REG_MHL_CBUS_23, BIT(13), BIT(13)}, // [13]: send rcv_pkt_msc_sw_overwrite_err_in mask
192 {REG_MHL_CBUS_24, BIT(1), BIT(1)}, // [1]: send error interrupt mask
193 …{REG_MHL_CBUS_25, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: response_pkt_msc_hw_int mas…
194 {REG_MHL_CBUS_63, BIT(9), BIT(9)}, // [9]: dytycycle_bad_int mask
195 …{REG_MHL_CBUS_65, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: rcv_parity_err_int mask, [5…
196 …{REG_MHL_CBUS_78, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mas…
213 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
221 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
409 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
411 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
418 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
430 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
432 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
433 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
434 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
439 W2BYTEMSK(REG_COMBO_PHY0_P1_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
451 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
453 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
454 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
455 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
460 W2BYTEMSK(REG_COMBO_PHY0_P2_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
472 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
474 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
475 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
476 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
481 W2BYTEMSK(REG_COMBO_PHY0_P3_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
515 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
517 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
518 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
519 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
525 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
537 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
539 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
540 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
541 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
547 W2BYTEMSK(REG_COMBO_PHY0_P1_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
559 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
561 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
562 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
563 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
569 W2BYTEMSK(REG_COMBO_PHY0_P2_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
581 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
583 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
584 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
585 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
591 W2BYTEMSK(REG_COMBO_PHY0_P3_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
625 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
626 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
636 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
637 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
647 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
648 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
658 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
659 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
692 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
696 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
697 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
702 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
716 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
720 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
721 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
726 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(4), BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
740 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
744 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
745 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
750 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
768 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
769 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
774 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(12), BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
799 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
800 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode in _mhal_mhl_CbusForceToStandby()
815 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14)); in _mhal_mhl_MHLForceToAttach()
837 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
847 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
857 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
867 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
992 if((R2BYTE(REG_COMBO_PHY0_P0_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1012 if((R2BYTE(REG_COMBO_PHY0_P1_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1032 if((R2BYTE(REG_COMBO_PHY0_P2_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1052 if((R2BYTE(REG_COMBO_PHY0_P3_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1092 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1102 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1112 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1122 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
1203 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(6)| BIT(8)| BIT(0)); // [0]: reg_hplugc_mhl_en in _mhal_mhl_CbusAndClockSelect()
1226 W2BYTEMSK(REG_PM_MHL_CBUS_20, bEnable? BIT(7): 0, BIT(7)); in _mhal_mhl_ForcePullDown100K()
1243 MS_U8 ucCommand = BIT(7) |BIT(6) |((ucOpCode &BMASK(2:0)) << 2); in _mhal_mhl_GetEMSCOneByteCRC()
1245 … ucAValue = GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BIT(3)) +2; in _mhal_mhl_GetEMSCOneByteCRC()
1246 … ucBValue = GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(4)) +GET_BIT(ucCommand &BIT(2)) +2; in _mhal_mhl_GetEMSCOneByteCRC()
1248 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCOneByteCRC()
1250 ucCommand |= BIT(1); in _mhal_mhl_GetEMSCOneByteCRC()
1253 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCOneByteCRC()
1255 ucCommand |= BIT(0); in _mhal_mhl_GetEMSCOneByteCRC()
1276 …MS_U16 ucCommand = BIT(13) |(((MS_U16)ucOpCode &BMASK(1:0)) << 11) |(((MS_U16)ucValue &BMASK(7:0))… in _mhal_mhl_GetEMSCTwoByteCRC()
1278 …T_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1279 …ucAValue = ucAValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BI… in _mhal_mhl_GetEMSCTwoByteCRC()
1280 …T_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1281 …ucBValue = ucBValue +GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BI… in _mhal_mhl_GetEMSCTwoByteCRC()
1282 …T_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1283 ucCValue = ucCValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +2; in _mhal_mhl_GetEMSCTwoByteCRC()
1285 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1287 ucCommand |= BIT(2); in _mhal_mhl_GetEMSCTwoByteCRC()
1290 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1292 ucCommand |= BIT(1); in _mhal_mhl_GetEMSCTwoByteCRC()
1295 if(ucCValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1297 ucCommand |= BIT(0); in _mhal_mhl_GetEMSCTwoByteCRC()
1317 …U8 ucCValue = GET_BIT(ucOpCode &BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(usCRCValus &BIT(6)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1318 …U8 ucDValue = GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(usCRCValus &BIT(5)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1319 …U8 ucEValue = GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(usCRCValus &BIT(4)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1320 …U8 ucFValue = GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(usCRCValus &BIT(3)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1321 …U8 ucGValue = GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(usCRCValus &BIT(2)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1322 …U8 ucHValue = GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(usCRCValus &BIT(1)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1323 …GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCVa… in _mhal_mhl_GetEMSCPayloadCRC()
1324 …MS_U8 ucJValue = GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1… in _mhal_mhl_GetEMSCPayloadCRC()
1325 MS_U8 ucKValue = GET_BIT(usCRCValus &BIT(13)); in _mhal_mhl_GetEMSCPayloadCRC()
1326 MS_U8 ucLValue = GET_BIT(usCRCValus &BIT(12)); in _mhal_mhl_GetEMSCPayloadCRC()
1327 MS_U8 ucMValue = GET_BIT(usCRCValus &BIT(11)); in _mhal_mhl_GetEMSCPayloadCRC()
1328 MS_U8 ucNValue = GET_BIT(usCRCValus &BIT(10)); in _mhal_mhl_GetEMSCPayloadCRC()
1329 MS_U8 ucOValue = GET_BIT(usCRCValus &BIT(9)); in _mhal_mhl_GetEMSCPayloadCRC()
1333 …BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(… in _mhal_mhl_GetEMSCPayloadCRC()
1334 …BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GE… in _mhal_mhl_GetEMSCPayloadCRC()
1335 …BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(… in _mhal_mhl_GetEMSCPayloadCRC()
1336 …BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GE… in _mhal_mhl_GetEMSCPayloadCRC()
1337 ucPValue = ucAValue +GET_BIT(usCRCValus &BIT(8)); in _mhal_mhl_GetEMSCPayloadCRC()
1339 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1341 usCommand |= BIT(15); in _mhal_mhl_GetEMSCPayloadCRC()
1344 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1346 usCommand |= BIT(14); in _mhal_mhl_GetEMSCPayloadCRC()
1349 if(ucCValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1351 usCommand |= BIT(13); in _mhal_mhl_GetEMSCPayloadCRC()
1354 if(ucDValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1356 usCommand |= BIT(12); in _mhal_mhl_GetEMSCPayloadCRC()
1359 if(ucEValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1361 usCommand |= BIT(11); in _mhal_mhl_GetEMSCPayloadCRC()
1364 if(ucFValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1366 usCommand |= BIT(10); in _mhal_mhl_GetEMSCPayloadCRC()
1369 if(ucGValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1371 usCommand |= BIT(9); in _mhal_mhl_GetEMSCPayloadCRC()
1374 if(ucHValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1376 usCommand |= BIT(8); in _mhal_mhl_GetEMSCPayloadCRC()
1379 if(ucIValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1381 usCommand |= BIT(7); in _mhal_mhl_GetEMSCPayloadCRC()
1384 if(ucJValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1386 usCommand |= BIT(6); in _mhal_mhl_GetEMSCPayloadCRC()
1389 if(ucKValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1391 usCommand |= BIT(5); in _mhal_mhl_GetEMSCPayloadCRC()
1394 if(ucLValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1396 usCommand |= BIT(4); in _mhal_mhl_GetEMSCPayloadCRC()
1399 if(ucMValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1401 usCommand |= BIT(3); in _mhal_mhl_GetEMSCPayloadCRC()
1404 if(ucNValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1406 usCommand |= BIT(2); in _mhal_mhl_GetEMSCPayloadCRC()
1409 if(ucOValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1411 usCommand |= BIT(1); in _mhal_mhl_GetEMSCPayloadCRC()
1414 if(ucPValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1416 usCommand |= BIT(0); in _mhal_mhl_GetEMSCPayloadCRC()
1445 W2BYTEMSK(REG_MHL_ECBUS_PHY_78, BIT(0), BIT(0)); in _mhal_mhl_ECbusInitialSetting()
1448 W2BYTEMSK(REG_MHL_ECBUS_2D, BIT(3), BIT(3)); in _mhal_mhl_ECbusInitialSetting()
1451 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
1455 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7] in _mhal_mhl_ECbusInitialSetting()
1456 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5)); in _mhal_mhl_ECbusInitialSetting()
1465 …W2BYTEMSK(REG_MHL_ECBUS_79, BIT(11)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 1) << 3)| (_mhal_mhl_GetEMSCT… in _mhal_mhl_ECbusInitialSetting()
1466 W2BYTEMSK(REG_MHL_ECBUS_PHY_13, BIT(4), BIT(4)); // in _mhal_mhl_ECbusInitialSetting()
1467 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, BIT(11), BIT(11)); // in _mhal_mhl_ECbusInitialSetting()
1487 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time in _mhal_mhl_ECbusInitialSetting()
1492 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x33, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1495 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1498 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(8), BIT(8)); in _mhal_mhl_ECbusInitialSetting()
1519 W2BYTEMSK(REG_MHL_ECBUS_36, 0, BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1523 W2BYTEMSK(REG_MHL_ECBUS_36, BIT(0), BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1526 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1541 W2BYTEMSK(REG_MHL_ECBUS_36, bEnableFlag? 0: BIT(12), BIT(12)); // eMSC receive int mask in _mhal_mhl_SetEMSCReceiveInterrupt()
1542 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, bEnableFlag? 0: BIT(0), BIT(0)); // ECbus PLL pd in _mhal_mhl_ECbusEnableSetting()
1574 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
1575 W2BYTEMSK(REG_MHL_ECBUS_PHY_6F, bEnableFlag? BIT(8): 0, BIT(8)); // ECbus clock detect in _mhal_mhl_ECbusEnableSetting()
1576 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1577 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1581 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(13), BIT(13)); // [13]: ECbus on in _mhal_mhl_ECbusEnableSetting()
1585 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off in _mhal_mhl_ECbusEnableSetting()
1601 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
1616 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(0), BIT(0)); in _mhal_mhl_CbusEngineReset()
1617 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(0)); in _mhal_mhl_CbusEngineReset()
1673 W2BYTEMSK(REG_COMBO_PHY0_P0_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1685 W2BYTEMSK(REG_COMBO_PHY0_P1_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1697 W2BYTEMSK(REG_COMBO_PHY0_P2_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1709 W2BYTEMSK(REG_COMBO_PHY0_P3_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1743 if(R2BYTE(REG_MHL_ECBUS_PHY_4D) & BIT(15)) in _mhal_mhl_ECbusStateChangeProc()
1748 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4] in _mhal_mhl_ECbusStateChangeProc()
1764 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));// in _mhal_mhl_ECbusStateChangeProc()
1768 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay in _mhal_mhl_ECbusStateChangeProc()
1792 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1793 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1797 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeUpProc()
1815 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeDownProc()
1830 …W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_c… in _mhal_mhl_MHL3MuxSetting0()
1845 W2BYTEMSK(REG_MHL_ECBUS_23, BIT(15), BIT(15)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1847 while((R2BYTE(REG_MHL_ECBUS_23) & BIT(14)) == BIT(14)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1866 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1868 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
1895 if(usECbusData[ustemp] &BIT(15)) // Send case in _mhal_mhl_ParsingECbusCommand()
1899 if(usECbusData[usCounnter] &BIT(15)) in _mhal_mhl_ParsingECbusCommand()
1941 if((usECbusData[usCounnter] &BIT(15)) == 0) in _mhal_mhl_ParsingECbusCommand()
2026 usECbusCData[ustemp] = ucSendData |BIT(15); in _mhal_mhl_GetECbusCommand()
2320 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2340 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2350 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2457 if((R2BYTE(REG_DVI_DTOP_DUAL_P0_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2467 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2469 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2518 if((R2BYTE(REG_DVI_DTOP_DUAL_P1_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2528 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2530 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2579 if((R2BYTE(REG_DVI_DTOP_DUAL_P2_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2589 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2591 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2640 if((R2BYTE(REG_DVI_DTOP_DUAL_P3_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2650 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2652 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2722 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2726 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2749 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2753 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2766 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2770 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2807 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2838 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2859 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2890 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5)); in mhal_mhl_CbusFloating()
2894 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5)); in mhal_mhl_CbusFloating()
2912 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2916 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2919 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag in mhal_mhl_CbusStucktoLow()
2936 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2940 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2943 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag in mhal_mhl_CbusWakeupInterrupt()
2980 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2986 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2987 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2988 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
2991 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3017 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3018 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3019 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
3098 W2BYTEMSK(0x2B28, 0, BIT(11)); in mhal_mhl_initial()
3111 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3148 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3168 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3178 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3214 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3215 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3219 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3230 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3254 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3255 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3259 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3270 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3284 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3285 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3289 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3300 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3444 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3448 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
3466 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusStucktoLowFlag()
3470 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); in mhal_mhl_CbusStucktoLowFlag()
3488 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(7)) ?TRUE: FALSE); in mhal_mhl_CbusWakeupIntFlag()
3492 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); in mhal_mhl_CbusWakeupIntFlag()
3510 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(0)) ?TRUE: FALSE); in mhal_mhl_GetECbusStateChangeFlag()
3514 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
3534 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(12)) ?TRUE: FALSE); in mhal_mhl_GetEMSCReceiveFlag()
3538 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
3558 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(10)) // eMSC send pass interrupt. in mhal_mhl_GetEMSCSendStatus()
3560 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
3564 else if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(9)) // eMSC send fail interrupt. in mhal_mhl_GetEMSCSendStatus()
3566 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
3601 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send in mhal_mhl_CBusWrite()
3606 if((pdatabuf->databuf[uctemp]) &BIT(8)) in mhal_mhl_CBusWrite()
3636 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12)); in mhal_mhl_Cbus_SetPathEn()
3640 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13)); in mhal_mhl_Cbus_SetPathEn()
3670 if(!(reg_val &BIT(8))) // Received data in mhal_mhl_CbusIntCB()
3682 if(reg_val & BIT(15)) in mhal_mhl_CbusIntCB()
3688 *bIsCmdInData = (reg_val & BIT(8)) ? TRUE : FALSE; in mhal_mhl_CbusIntCB()
3704 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
4058 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4096 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4111 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4113 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
4135 W2BYTEMSK(0x001106, BIT(10), BIT(10)); in mhal_mhl_TestSignal()
4139 W2BYTEMSK(0x001106, 0, BIT(10)); in mhal_mhl_TestSignal()
4267 if(R2BYTE(REG_MHL_ECBUS_PHY_6F) &BIT(13)) // [13]: ECbus clock lock flag in mhal_mhl_GetECbusStatusFlag()
4276 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13)); in mhal_mhl_GetECbusStatusFlag()
4280 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(7)) // REG_MHL_CBUS2_3A[7] in mhal_mhl_GetECbusStatusFlag()
4285 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(15)) // REG_MHL_CBUS2_3A[15] in mhal_mhl_GetECbusStatusFlag()
4430 W2BYTEMSK(REG_MHL_ECBUS_1C, BIT(15), BIT(15)); in mhal_mhl_GetEMSCReceiveData()
4454 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
4465 W2BYTEMSK(REG_MHL_ECBUS_19, BIT(15), BIT(15)); // eMSC payload CRC ove in mhal_mhl_InsertEMSCSendData()
4470 W2BYTEMSK(REG_MHL_ECBUS_1B, BIT(15), BIT(15)); // REG_MHL_ECBUS2_1B[15] in mhal_mhl_InsertEMSCSendData()