Lines Matching refs:BIT
145 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
146 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
148 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
157 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
160 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
162 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
165 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
169 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
174 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
175 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
176 {REG_PM_MHL_CBUS_30, BIT(1), BIT(1)}, // [1]: cbus conflict_int mask
177 …{REG_PM_MHL_CBUS_38, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused …
178 {REG_MHL_CBUS_14, BIT(13), BIT(13)}, // [13]: int mask for monitor_sram_full
179 {REG_MHL_CBUS_18, BIT(13), BIT(13)}, // [13]: send rcv_pkt_ddc_sw_overwrite_err_in mask
180 …{REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1…
181 {REG_MHL_CBUS_1B, BIT(1), BIT(1)}, // [1]: receive ddc packet valid mask
182 …{REG_MHL_CBUS_1F, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: ddc access edid timeout int mask, [1]: cl…
183 {REG_MHL_CBUS_21, BIT(5), BIT(5)}, // [5]: ddc error interrupt mask
184 …{REG_MHL_CBUS_22, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: ddc access hdcp timeout int…
185 {REG_MHL_CBUS_23, BIT(13), BIT(13)}, // [13]: send rcv_pkt_msc_sw_overwrite_err_in mask
186 {REG_MHL_CBUS_24, BIT(1), BIT(1)}, // [1]: send error interrupt mask
187 …{REG_MHL_CBUS_25, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: response_pkt_msc_hw_int mas…
188 {REG_MHL_CBUS_63, BIT(9), BIT(9)}, // [9]: dytycycle_bad_int mask
189 …{REG_MHL_CBUS_65, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: rcv_parity_err_int mask, [5…
190 …{REG_MHL_CBUS_78, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mas…
207 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
215 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
259 if((R2BYTE(REG_DVI_DTOP_2F_L) &BIT(0)) == BIT(0)) in _mhal_mhl_DviAutoEQSwitch()
269 W2BYTEMSK(REG_DVI_DTOP_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
270 W2BYTEMSK(REG_DVI_DTOP_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
274 W2BYTEMSK(REG_DVI_DTOP_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
275 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
289 if((R2BYTE(REG_DVI_DTOP1_2F_L) &BIT(0)) == BIT(0)) in _mhal_mhl_DviAutoEQSwitch()
299 W2BYTEMSK(REG_DVI_DTOP1_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
300 W2BYTEMSK(REG_DVI_DTOP1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
304 W2BYTEMSK(REG_DVI_DTOP1_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
305 W2BYTEMSK(REG_DVI_DTOP1_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
319 if((R2BYTE(REG_DVI_DTOP3_2F_L) &BIT(0)) == BIT(0)) in _mhal_mhl_DviAutoEQSwitch()
329 W2BYTEMSK(REG_DVI_DTOP3_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
330 W2BYTEMSK(REG_DVI_DTOP3_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
334 W2BYTEMSK(REG_DVI_DTOP3_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
335 W2BYTEMSK(REG_DVI_DTOP3_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
349 if((R2BYTE(REG_DVI_DTOP2_2F_L) &BIT(0)) == BIT(0)) in _mhal_mhl_DviAutoEQSwitch()
359 W2BYTEMSK(REG_DVI_DTOP2_00_L, BIT(4), BIT(4)); // enable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
360 W2BYTEMSK(REG_DVI_DTOP2_2F_L, BIT(0), BIT(0)); // enable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
364 W2BYTEMSK(REG_DVI_DTOP2_00_L, 0, BIT(4)); // disable EQ new mode in _mhal_mhl_DviAutoEQSwitch()
365 W2BYTEMSK(REG_DVI_DTOP2_2F_L, 0, BIT(0)); // disable autoEQ controller in _mhal_mhl_DviAutoEQSwitch()
399 W2BYTEMSK(REG_DVI_DTOP_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
400 W2BYTEMSK(REG_DVI_DTOP_3B_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
401 W2BYTEMSK(REG_DVI_DTOP_3D_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
402 W2BYTEMSK(REG_DVI_DTOP_3F_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
405 …W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypa… in _mhal_mhl_HdmiBypassModeSetting()
406 …W2BYTEMSK(REG_DVI_ATOP_38_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable a… in _mhal_mhl_HdmiBypassModeSetting()
408 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
409 W2BYTEMSK(REG_HDCP_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_DVI_DTOP_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
426 W2BYTEMSK(REG_DVI_DTOP1_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
427 W2BYTEMSK(REG_DVI_DTOP1_3B_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
428 W2BYTEMSK(REG_DVI_DTOP1_3D_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
429 W2BYTEMSK(REG_DVI_DTOP1_3F_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
430 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
432 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BIT(7)); // power on DVI PLL in _mhal_mhl_HdmiBypassModeSetting()
433 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
436 W2BYTEMSK(REG_HDCP1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
440 W2BYTEMSK(REG_DVI_DTOP1_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
453 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
454 W2BYTEMSK(REG_DVI_DTOP3_3B_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
455 W2BYTEMSK(REG_DVI_DTOP3_3D_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
456 W2BYTEMSK(REG_DVI_DTOP3_3F_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
459 …W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
460 …W2BYTEMSK(REG_DVI_ATOP3_35_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable … in _mhal_mhl_HdmiBypassModeSetting()
462 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
463 W2BYTEMSK(REG_HDCP3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
467 W2BYTEMSK(REG_DVI_DTOP3_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
480 W2BYTEMSK(REG_DVI_DTOP2_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
481 W2BYTEMSK(REG_DVI_DTOP2_3B_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
482 W2BYTEMSK(REG_DVI_DTOP2_3D_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
483 W2BYTEMSK(REG_DVI_DTOP2_3F_L, 0, BIT(4)); // overwirte enable in _mhal_mhl_HdmiBypassModeSetting()
486 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Byp… in _mhal_mhl_HdmiBypassModeSetting()
487 …W2BYTEMSK(REG_DVI_ATOP2_35_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable … in _mhal_mhl_HdmiBypassModeSetting()
489 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_HdmiBypassModeSetting()
490 W2BYTEMSK(REG_HDCP2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
494 W2BYTEMSK(REG_DVI_DTOP2_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
527 W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_Mhl24bitsModeSetting()
529 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
531 W2BYTEMSK(REG_DVI_DTOP_3B_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
533 W2BYTEMSK(REG_DVI_DTOP_3D_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
535 W2BYTEMSK(REG_DVI_DTOP_3F_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
538 …W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, E… in _mhal_mhl_Mhl24bitsModeSetting()
539 …W2BYTEMSK(REG_DVI_ATOP_38_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection,… in _mhal_mhl_Mhl24bitsModeSetting()
540 …W2BYTEMSK(REG_DVI_ATOP_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL value… in _mhal_mhl_Mhl24bitsModeSetting()
541 W2BYTEMSK(REG_HDCP_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
545 W2BYTEMSK(REG_DVI_DTOP_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
556 W2BYTEMSK(REG_DVI_DTOP1_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL in _mhal_mhl_Mhl24bitsModeSetting()
558 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
560 W2BYTEMSK(REG_DVI_DTOP1_3B_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
562 W2BYTEMSK(REG_DVI_DTOP1_3D_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
564 W2BYTEMSK(REG_DVI_DTOP1_3F_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
565 …W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
566 …W2BYTEMSK(REG_DVI_ATOP1_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICT… in _mhal_mhl_Mhl24bitsModeSetting()
569 W2BYTEMSK(REG_HDCP1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
573 W2BYTEMSK(REG_DVI_DTOP1_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
584 …W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, … in _mhal_mhl_Mhl24bitsModeSetting()
586 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
588 W2BYTEMSK(REG_DVI_DTOP3_3B_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
590 W2BYTEMSK(REG_DVI_DTOP3_3D_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
592 W2BYTEMSK(REG_DVI_DTOP3_3F_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
595 …W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
596 …W2BYTEMSK(REG_DVI_ATOP3_35_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection… in _mhal_mhl_Mhl24bitsModeSetting()
597 …W2BYTEMSK(REG_DVI_ATOP3_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL valu… in _mhal_mhl_Mhl24bitsModeSetting()
598 W2BYTEMSK(REG_HDCP3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
602 W2BYTEMSK(REG_DVI_DTOP3_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
613 …W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, … in _mhal_mhl_Mhl24bitsModeSetting()
615 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); // auto clear phase accumulator in _mhal_mhl_Mhl24bitsModeSetting()
617 W2BYTEMSK(REG_DVI_DTOP2_3B_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
619 W2BYTEMSK(REG_DVI_DTOP2_3D_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
621 W2BYTEMSK(REG_DVI_DTOP2_3F_L, BIT(4), BIT(4)); // overwirte enable in _mhal_mhl_Mhl24bitsModeSetting()
624 …W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, … in _mhal_mhl_Mhl24bitsModeSetting()
625 …W2BYTEMSK(REG_DVI_ATOP2_35_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection… in _mhal_mhl_Mhl24bitsModeSetting()
626 …W2BYTEMSK(REG_DVI_ATOP2_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICT… in _mhal_mhl_Mhl24bitsModeSetting()
627 W2BYTEMSK(REG_HDCP2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
631 W2BYTEMSK(REG_DVI_DTOP2_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
666 W2BYTEMSK(REG_HDCP_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
678 W2BYTEMSK(REG_HDCP1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
690 W2BYTEMSK(REG_HDCP3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
702 W2BYTEMSK(REG_HDCP2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
735 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
740 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
745 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
769 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(9), BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
783 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
788 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
793 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(11), BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
807 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term in _mhal_mhl_RxRtermControl()
812 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term in _mhal_mhl_RxRtermControl()
817 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(10), BIT(10));// clock R-term in _mhal_mhl_RxRtermControl()
842 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
843 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode in _mhal_mhl_CbusForceToStandby()
858 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14)); in _mhal_mhl_MHLForceToAttach()
880 W2BYTEMSK(REG_DVI_DTOP_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable in _mhal_mhl_AdjustCommonModeResistor()
890 W2BYTEMSK(REG_DVI_DTOP1_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable in _mhal_mhl_AdjustCommonModeResistor()
900 W2BYTEMSK(REG_DVI_DTOP3_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable in _mhal_mhl_AdjustCommonModeResistor()
910 W2BYTEMSK(REG_DVI_DTOP2_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable in _mhal_mhl_AdjustCommonModeResistor()
944 bindex = ((R2BYTE(REG_DVI_ATOP_70_L) &BIT(0)) ?TRUE: FALSE); in _mhal_mhl_ClockBigChangeFlag()
948 W2BYTEMSK(REG_DVI_ATOP_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
949 W2BYTEMSK(REG_DVI_ATOP_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
960 bindex = ((R2BYTE(REG_DVI_ATOP1_70_L) &BIT(0)) ?TRUE: FALSE); in _mhal_mhl_ClockBigChangeFlag()
964 W2BYTEMSK(REG_DVI_ATOP1_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
965 W2BYTEMSK(REG_DVI_ATOP1_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
976 bindex = ((R2BYTE(REG_DVI_ATOP3_70_L) &BIT(0)) ?TRUE: FALSE); in _mhal_mhl_ClockBigChangeFlag()
980 W2BYTEMSK(REG_DVI_ATOP3_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
981 W2BYTEMSK(REG_DVI_ATOP3_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
992 bindex = ((R2BYTE(REG_DVI_ATOP2_70_L) &BIT(0)) ?TRUE: FALSE); in _mhal_mhl_ClockBigChangeFlag()
996 W2BYTEMSK(REG_DVI_ATOP2_71_L, BIT(8), BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
997 W2BYTEMSK(REG_DVI_ATOP2_71_L, 0, BIT(8)); in _mhal_mhl_ClockBigChangeFlag()
1035 if((R2BYTE(REG_DVI_DTOP_16_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1055 if((R2BYTE(REG_DVI_DTOP1_16_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1075 if((R2BYTE(REG_DVI_DTOP3_16_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1095 if((R2BYTE(REG_DVI_DTOP2_16_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1135 W2BYTEMSK(REG_DVI_ATOP_7F_L, bFlag ?BIT(14) :0, BIT(14)); in _mhal_mhl_RtermHWControl()
1155 W2BYTEMSK(REG_DVI_ATOP3_01_L, bFlag ?BIT(0) :0, BIT(0)); in _mhal_mhl_RtermHWControl()
1165 W2BYTEMSK(REG_DVI_ATOP2_00_L, bFlag ?BIT(0) :0, BIT(0)); in _mhal_mhl_RtermHWControl()
1219 …W2BYTEMSK(REG_HDMI2_08_L, bMHLPath ?BIT(0) :0, BIT(0)); // [0]: audio source selection, 0: HDMI / … in _mhal_mhl_AudioPathSelect()
1246 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(6)| BIT(8)| BIT(0)); // [0]: reg_hplugc_mhl_en in _mhal_mhl_CbusAndClockSelect()
1251 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(8), BIT(14)| BIT(8)| BIT(0)); // [8]: reg_hpluga_mhl_en in _mhal_mhl_CbusAndClockSelect()
1276 … W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria in _mhal_mhl_PhyInitialSetting()
1277 W2BYTEMSK(REG_DVI_DTOP_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2 in _mhal_mhl_PhyInitialSetting()
1297 … W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria in _mhal_mhl_PhyInitialSetting()
1298 W2BYTEMSK(REG_DVI_DTOP3_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2 in _mhal_mhl_PhyInitialSetting()
1308 … W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria in _mhal_mhl_PhyInitialSetting()
1309 W2BYTEMSK(REG_DVI_DTOP2_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2 in _mhal_mhl_PhyInitialSetting()
1582 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
1602 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
1612 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
1643 if(R2BYTE(REG_DVI_DTOP_16_L) & BIT(9)) // clk stable in mhal_mhl_Accumulator_Clr()
1649 W2BYTEMSK(REG_DVI_DTOP_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1650 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
1662 if(R2BYTE(REG_DVI_DTOP1_16_L) & BIT(9)) // clk stable in mhal_mhl_Accumulator_Clr()
1668 W2BYTEMSK(REG_DVI_DTOP1_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1669 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
1681 if(R2BYTE(REG_DVI_DTOP3_16_L) & BIT(9)) // clk stable in mhal_mhl_Accumulator_Clr()
1687 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1688 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
1700 if(R2BYTE(REG_DVI_DTOP2_16_L) & BIT(9)) // clk stable in mhal_mhl_Accumulator_Clr()
1706 W2BYTEMSK(REG_DVI_DTOP2_0E_L, BIT(4), BIT(4)); // clear accumulator in mhal_mhl_Accumulator_Clr()
1707 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); in mhal_mhl_Accumulator_Clr()
1750 if((R2BYTE(REG_DVI_DTOP_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
1754 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12)); in mhal_mhl_CDRModeMonitor()
1755 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12)); in mhal_mhl_CDRModeMonitor()
1807 if((R2BYTE(REG_DVI_DTOP3_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
1811 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12)); in mhal_mhl_CDRModeMonitor()
1812 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12)); in mhal_mhl_CDRModeMonitor()
1854 if((R2BYTE(REG_DVI_DTOP2_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
1858 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12)); in mhal_mhl_CDRModeMonitor()
1859 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12)); in mhal_mhl_CDRModeMonitor()
1927 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1931 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1954 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1958 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1971 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
1975 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2012 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2043 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2064 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2095 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5)); in mhal_mhl_CbusFloating()
2099 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5)); in mhal_mhl_CbusFloating()
2117 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2121 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2124 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag in mhal_mhl_CbusStucktoLow()
2141 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2145 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2148 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag in mhal_mhl_CbusWakeupInterrupt()
2185 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
2191 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
2192 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
2193 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
2196 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
2222 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
2223 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
2224 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
2295 W2BYTEMSK(0x2B28, 0, BIT(11)); in mhal_mhl_initial()
2308 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
2322 W2BYTEMSK(0x001102, BIT(7), BIT(7)); in mhal_mhl_initial()
2323 W2BYTEMSK(0x001128, BIT(0), BIT(0)); in mhal_mhl_initial()
2350 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
2370 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
2380 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
2416 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2417 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2421 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2432 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2456 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2457 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2461 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2472 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2486 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2487 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
2491 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
2502 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
2653 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
2657 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
2675 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusStucktoLowFlag()
2679 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); in mhal_mhl_CbusStucktoLowFlag()
2697 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(7)) ?TRUE: FALSE); in mhal_mhl_CbusWakeupIntFlag()
2701 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); in mhal_mhl_CbusWakeupIntFlag()
2734 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send in mhal_mhl_CBusWrite()
2754 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12)); in mhal_mhl_Cbus_SetPathEn()
2758 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13)); in mhal_mhl_Cbus_SetPathEn()
2788 if(!(reg_val &BIT(8))) // Received data in mhal_mhl_CbusIntCB()
2800 if(reg_val & BIT(15)) in mhal_mhl_CbusIntCB()
2806 *bIsCmdInData = (reg_val & BIT(8)) ? TRUE : FALSE; in mhal_mhl_CbusIntCB()
2822 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
2841 if(R2BYTE(REG_HDMI_04_L) &BIT(1)) in mhal_mhl_CBusCheckBCHError()
2845 W2BYTEMSK(REG_HDMI_04_L, BIT(1), BIT(1)); in mhal_mhl_CBusCheckBCHError()
3160 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(0)); // [0]: reg_hplugc_mhl_en in mhal_mhl_SetHPD()
3164 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
3202 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
3217 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
3219 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
3241 W2BYTEMSK(0x001106, BIT(10), BIT(10)); in mhal_mhl_TestSignal()
3245 W2BYTEMSK(0x001106, 0, BIT(10)); in mhal_mhl_TestSignal()