1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ///////////////////////////////////////////////////////////////////////////////////////////////////
79 ///
80 /// file mhal_mhl.c
81 /// @author MStar Semiconductor Inc.
82 /// @brief MHL driver Function
83 ///////////////////////////////////////////////////////////////////////////////////////////////////
84
85 #ifndef _MHAL_MHL_C_
86 #define _MHAL_MHL_C_
87
88 //-------------------------------------------------------------------------------------------------
89 // Include Files
90 //-------------------------------------------------------------------------------------------------
91 // Common Definition
92 #include "MsCommon.h"
93 #include "MsVersion.h"
94 #ifdef MSOS_TYPE_LINUX_KERNEL
95 #include <linux/string.h>
96 #else
97 #include <string.h>
98 #endif
99 #include "MsIRQ.h"
100 #include "MsOS.h"
101 #include "mhal_xc_chip_config.h"
102 #include "mhl_hwreg_utility2.h"
103 #include "hwreg_pm_sleep.h"
104 #include "hwreg_hdmi.h"
105 #include "hwreg_hdcp.h"
106 #include "hwregMHL.h"
107 #include "mdrv_mhl_st.h"
108 #include "halMHL.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Local Defines
112 //-------------------------------------------------------------------------------------------------
113 #define msg_mhl(x) x
114
115 #define DMHLInit 0
116
117 //-------------------------------------------------------------------------------------------------
118 // Local Structures
119 //-------------------------------------------------------------------------------------------------
120 typedef struct
121 {
122 MS_U32 addr;
123 MS_U16 mask;
124 MS_U16 databuf;
125 } msLoadTbl_S;
126
127 //-------------------------------------------------------------------------------------------------
128 // Global Variables
129 //-------------------------------------------------------------------------------------------------
130 MS_BOOL bMHLSignalStable = FALSE;
131 MS_U8 ucMHLSupportPort = E_MUX_NOT_SUPPORT_MHL;
132 MS_U8 ucIControlValue = MHL_ICONTROL_VALUE;
133 MS_U8 ucImpedanceValue = MHL_IMPEDANCE_VALUE;
134 MS_U8 ucChipIDValue = MHL_CHIP_ID_MUSTANG;
135
136 //-------------------------------------------------------------------------------------------------
137 // MHL initial table
138 //-------------------------------------------------------------------------------------------------
139 static msLoadTbl_S tMHL_INITIAL_TABLE[] =
140 {
141 // Set accepted discover pulse high pulse width to ignore USB pulse
142 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
143 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
144 // CTS 4.3.7.1
145 {REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitration
146 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
147
148 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
149
150 // For CTS 6.3.10.7
151 {REG_MHL_CBUS_59, BMASK(15:0), 0xADB0}, // timeout for a device receiving a packet within a command
152 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 110ms
153
154 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
155
156 #if(MHL_CBUS_OPERATION_MODE >= MHL_CBUS_HW_ISR_MODE)
157 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_devcap request
158 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
159 {REG_MHL_CBUS_71, BMASK(15:14), BMASK(15:14)},
160 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
161 #else
162 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
163 {REG_MHL_CBUS_6D, BMASK(11:0), 0}, // Enable MHL HW mode
164 {REG_MHL_CBUS_71, BMASK(15:14), 0},
165 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
166 #endif
167
168 #if(MHL_CBUS_OPERATION_MODE == MHL_CBUS_HW_REPLY_MODE)
169 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
170 #endif
171
172 #if DMHL_INT_ENABLE
173 // Mask unused interrupt events
174 {REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_state_chg_int mask
175 {REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confirm_int mask, [5]: wakeup_pul_confirm_int mask, [1]: cbus_stuck_to_low_int mask.
176 {REG_PM_MHL_CBUS_30, BIT(1), BIT(1)}, // [1]: cbus conflict_int mask
177 {REG_PM_MHL_CBUS_38, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mask, [9]: unused mask, [5]: unused mask, [1]: unused mask.
178 {REG_MHL_CBUS_14, BIT(13), BIT(13)}, // [13]: int mask for monitor_sram_full
179 {REG_MHL_CBUS_18, BIT(13), BIT(13)}, // [13]: send rcv_pkt_ddc_sw_overwrite_err_in mask
180 {REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1]: send ddc error interrupt mask
181 {REG_MHL_CBUS_1B, BIT(1), BIT(1)}, // [1]: receive ddc packet valid mask
182 {REG_MHL_CBUS_1F, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: ddc access edid timeout int mask, [1]: client_wrt_ddc_ram interrupt mask
183 {REG_MHL_CBUS_21, BIT(5), BIT(5)}, // [5]: ddc error interrupt mask
184 {REG_MHL_CBUS_22, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: ddc access hdcp timeout int mask, [5]: receive nack pkt int_mask, [1]: receive abort pkt int mask
185 {REG_MHL_CBUS_23, BIT(13), BIT(13)}, // [13]: send rcv_pkt_msc_sw_overwrite_err_in mask
186 {REG_MHL_CBUS_24, BIT(1), BIT(1)}, // [1]: send error interrupt mask
187 {REG_MHL_CBUS_25, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: response_pkt_msc_hw_int mask, [5]: snd_pkt_msc_hw_int mask, [1]: msc sw send complete interrupt mask
188 {REG_MHL_CBUS_63, BIT(9), BIT(9)}, // [9]: dytycycle_bad_int mask
189 {REG_MHL_CBUS_65, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: rcv_parity_err_int mask, [5]: rcv_data_err_int mask, [1]: rcv_sync_err_int mask
190 {REG_MHL_CBUS_78, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mask, [9]: unused mask, [5]: unused mask, [1]: unused mask.
191 #endif
192 };
193
194 //-------------------------------------------------------------------------------------------------
195 // MHL power on table
196 //-------------------------------------------------------------------------------------------------
197 static msLoadTbl_S tMHL_POWER_ON_TABLE[] =
198 {
199 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
200 };
201
202 //-------------------------------------------------------------------------------------------------
203 // MHL power down table
204 //-------------------------------------------------------------------------------------------------
205 static msLoadTbl_S tMHL_POWER_DOWN_TABLE[] =
206 {
207 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
208 };
209
210 //-------------------------------------------------------------------------------------------------
211 // MHL power saving table
212 //-------------------------------------------------------------------------------------------------
213 static msLoadTbl_S tMHL_POWER_SAVING_TABLE[] =
214 {
215 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
216 };
217
218 //-------------------------------------------------------------------------------------------------
219 // Local Functions
220 //-------------------------------------------------------------------------------------------------
221
222 //**************************************************************************
223 // [Function Name]:
224 // _mhal_mhl_IsCbusBusy()
225 // [Description]
226 //
227 // [Arguments]:
228 //
229 // [Return]:
230 //
231 //**************************************************************************
_mhal_mhl_IsCbusBusy(void)232 MS_BOOL _mhal_mhl_IsCbusBusy(void)
233 {
234 return ((R2BYTE(REG_MHL_CBUS_5D) & 0x00F0) != 0 ? TRUE : FALSE);
235 }
236
237 //**************************************************************************
238 // [Function Name]:
239 // _mhal_mhl_DviAutoEQSwitch()
240 // [Description]
241 //
242 // [Arguments]:
243 //
244 // [Return]:
245 //
246 //**************************************************************************
_mhal_mhl_DviAutoEQSwitch(MS_U8 ucCbusSelect,MS_BOOL bFlag)247 void _mhal_mhl_DviAutoEQSwitch(MS_U8 ucCbusSelect, MS_BOOL bFlag)
248 {
249 static MS_BOOL bAutoEQFlag = FALSE;
250
251 switch(ucCbusSelect)
252 {
253 #if(MHL_FUNCTION_SUPPORT_PORTA)
254 case MHL_CBUS_SELECT_PORTA:
255 if(GET_MHL_PATH_SUPPORT_PORTA())
256 {
257 if(!bAutoEQFlag)
258 {
259 if((R2BYTE(REG_DVI_DTOP_2F_L) &BIT(0)) == BIT(0))
260 {
261 bAutoEQFlag = TRUE;
262 }
263 }
264
265 if(bAutoEQFlag)
266 {
267 if(bFlag)
268 {
269 W2BYTEMSK(REG_DVI_DTOP_00_L, BIT(4), BIT(4)); // enable EQ new mode
270 W2BYTEMSK(REG_DVI_DTOP_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
271 }
272 else
273 {
274 W2BYTEMSK(REG_DVI_DTOP_00_L, 0, BIT(4)); // disable EQ new mode
275 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BIT(0)); // disable autoEQ controller
276 }
277 }
278 }
279
280 break;
281 #endif
282
283 #if(MHL_FUNCTION_SUPPORT_PORTB)
284 case MHL_CBUS_SELECT_PORTB:
285 if(GET_MHL_PATH_SUPPORT_PORTB())
286 {
287 if(!bAutoEQFlag)
288 {
289 if((R2BYTE(REG_DVI_DTOP1_2F_L) &BIT(0)) == BIT(0))
290 {
291 bAutoEQFlag = TRUE;
292 }
293 }
294
295 if(bAutoEQFlag)
296 {
297 if(bFlag)
298 {
299 W2BYTEMSK(REG_DVI_DTOP1_00_L, BIT(4), BIT(4)); // enable EQ new mode
300 W2BYTEMSK(REG_DVI_DTOP1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
301 }
302 else
303 {
304 W2BYTEMSK(REG_DVI_DTOP1_00_L, 0, BIT(4)); // disable EQ new mode
305 W2BYTEMSK(REG_DVI_DTOP1_2F_L, 0, BIT(0)); // disable autoEQ controller
306 }
307 }
308 }
309
310 break;
311 #endif
312
313 #if(MHL_FUNCTION_SUPPORT_PORTC)
314 case MHL_CBUS_SELECT_PORTC:
315 if(GET_MHL_PATH_SUPPORT_PORTC())
316 {
317 if(!bAutoEQFlag)
318 {
319 if((R2BYTE(REG_DVI_DTOP3_2F_L) &BIT(0)) == BIT(0))
320 {
321 bAutoEQFlag = TRUE;
322 }
323 }
324
325 if(bAutoEQFlag)
326 {
327 if(bFlag)
328 {
329 W2BYTEMSK(REG_DVI_DTOP3_00_L, BIT(4), BIT(4)); // enable EQ new mode
330 W2BYTEMSK(REG_DVI_DTOP3_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
331 }
332 else
333 {
334 W2BYTEMSK(REG_DVI_DTOP3_00_L, 0, BIT(4)); // disable EQ new mode
335 W2BYTEMSK(REG_DVI_DTOP3_2F_L, 0, BIT(0)); // disable autoEQ controller
336 }
337 }
338 }
339
340 break;
341 #endif
342
343 #if(MHL_FUNCTION_SUPPORT_PORTD)
344 case MHL_CBUS_SELECT_PORTD:
345 if(GET_MHL_PATH_SUPPORT_PORTD())
346 {
347 if(!bAutoEQFlag)
348 {
349 if((R2BYTE(REG_DVI_DTOP2_2F_L) &BIT(0)) == BIT(0))
350 {
351 bAutoEQFlag = TRUE;
352 }
353 }
354
355 if(bAutoEQFlag)
356 {
357 if(bFlag)
358 {
359 W2BYTEMSK(REG_DVI_DTOP2_00_L, BIT(4), BIT(4)); // enable EQ new mode
360 W2BYTEMSK(REG_DVI_DTOP2_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
361 }
362 else
363 {
364 W2BYTEMSK(REG_DVI_DTOP2_00_L, 0, BIT(4)); // disable EQ new mode
365 W2BYTEMSK(REG_DVI_DTOP2_2F_L, 0, BIT(0)); // disable autoEQ controller
366 }
367 }
368 }
369
370 break;
371 #endif
372
373 default:
374
375 break;
376 };
377 }
378
379 //**************************************************************************
380 // [Function Name]:
381 // _mhal_mhl_HdmiBypassModeSetting()
382 // [Description]
383 // MHL HDMI bypass setting
384 // [Arguments]:
385 //
386 // [Return]:
387 //
388 //**************************************************************************
_mhal_mhl_HdmiBypassModeSetting(MS_U8 ucCbusSelect)389 void _mhal_mhl_HdmiBypassModeSetting(MS_U8 ucCbusSelect)
390 {
391 switch(ucCbusSelect)
392 {
393 #if(MHL_FUNCTION_SUPPORT_PORTA)
394 case MHL_CBUS_SELECT_PORTA:
395 if(GET_MHL_PATH_SUPPORT_PORTA())
396 {
397 W2BYTEMSK(REG_DVI_DTOP_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL
398 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
399 W2BYTEMSK(REG_DVI_DTOP_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator
400 W2BYTEMSK(REG_DVI_DTOP_3B_L, 0, BIT(4)); // overwirte enable
401 W2BYTEMSK(REG_DVI_DTOP_3D_L, 0, BIT(4)); // overwirte enable
402 W2BYTEMSK(REG_DVI_DTOP_3F_L, 0, BIT(4)); // overwirte enable
403 W2BYTE(REG_DVI_DTOP_30_L, 0);
404 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BMASK(15:4)| BMASK(3:2));
405 W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
406 W2BYTEMSK(REG_DVI_ATOP_38_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
407 W2BYTEMSK(REG_DVI_ATOP_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
408 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); // auto clear phase accumulator
409 W2BYTEMSK(REG_HDCP_09_L, 0, BIT(0)); // PP mode + HDCP eanble
410
411 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
412 {
413 W2BYTEMSK(REG_DVI_DTOP_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0));
414 }
415 }
416
417 break;
418 #endif
419
420 #if(MHL_FUNCTION_SUPPORT_PORTB)
421 case MHL_CBUS_SELECT_PORTB:
422 if(GET_MHL_PATH_SUPPORT_PORTB())
423 {
424 W2BYTEMSK(REG_DVI_DTOP1_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL
425 W2BYTEMSK(REG_DVI_DTOP1_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
426 W2BYTEMSK(REG_DVI_DTOP1_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator
427 W2BYTEMSK(REG_DVI_DTOP1_3B_L, 0, BIT(4)); // overwirte enable
428 W2BYTEMSK(REG_DVI_DTOP1_3D_L, 0, BIT(4)); // overwirte enable
429 W2BYTEMSK(REG_DVI_DTOP1_3F_L, 0, BIT(4)); // overwirte enable
430 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
431 W2BYTEMSK(REG_DVI_ATOP1_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
432 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BIT(7)); // power on DVI PLL
433 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); // auto clear phase accumulator
434 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(2:1)); // [2:0]: power down RD
435 W2BYTEMSK(REG_DVI_ATOP1_74_L, 0, BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power down DPLPHQ
436 W2BYTEMSK(REG_HDCP1_09_L, 0, BIT(0)); // PP mode + HDCP eanble
437
438 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
439 {
440 W2BYTEMSK(REG_DVI_DTOP1_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0));
441 }
442 }
443
444 break;
445 #endif
446
447 #if(MHL_FUNCTION_SUPPORT_PORTC)
448 case MHL_CBUS_SELECT_PORTC:
449 if(GET_MHL_PATH_SUPPORT_PORTC())
450 {
451 W2BYTEMSK(REG_DVI_DTOP3_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL
452 W2BYTEMSK(REG_DVI_DTOP3_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
453 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator
454 W2BYTEMSK(REG_DVI_DTOP3_3B_L, 0, BIT(4)); // overwirte enable
455 W2BYTEMSK(REG_DVI_DTOP3_3D_L, 0, BIT(4)); // overwirte enable
456 W2BYTEMSK(REG_DVI_DTOP3_3F_L, 0, BIT(4)); // overwirte enable
457 W2BYTE(REG_DVI_DTOP3_30_L, 0);
458 W2BYTEMSK(REG_DVI_DTOP3_2F_L, 0, BMASK(15:4)| BMASK(3:2));
459 W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
460 W2BYTEMSK(REG_DVI_ATOP3_35_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
461 W2BYTEMSK(REG_DVI_ATOP3_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
462 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator
463 W2BYTEMSK(REG_HDCP3_09_L, 0, BIT(0)); // PP mode + HDCP eanble
464
465 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
466 {
467 W2BYTEMSK(REG_DVI_DTOP3_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0));
468 }
469 }
470
471 break;
472 #endif
473
474 #if(MHL_FUNCTION_SUPPORT_PORTD)
475 case MHL_CBUS_SELECT_PORTD:
476 if(GET_MHL_PATH_SUPPORT_PORTD())
477 {
478 W2BYTEMSK(REG_DVI_DTOP2_27_L, 0x2C6C, BMASK(14:0)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, [0]: MHL enable
479 W2BYTEMSK(REG_DVI_DTOP2_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
480 W2BYTEMSK(REG_DVI_DTOP2_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator
481 W2BYTEMSK(REG_DVI_DTOP2_3B_L, 0, BIT(4)); // overwirte enable
482 W2BYTEMSK(REG_DVI_DTOP2_3D_L, 0, BIT(4)); // overwirte enable
483 W2BYTEMSK(REG_DVI_DTOP2_3F_L, 0, BIT(4)); // overwirte enable
484 W2BYTE(REG_DVI_DTOP2_30_L, 0);
485 W2BYTEMSK(REG_DVI_DTOP2_2F_L, 0, BMASK(15:4)| BMASK(3:2));
486 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
487 W2BYTEMSK(REG_DVI_ATOP2_35_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
488 W2BYTEMSK(REG_DVI_ATOP2_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
489 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); // auto clear phase accumulator
490 W2BYTEMSK(REG_HDCP2_09_L, 0, BIT(0)); // PP mode + HDCP eanble
491
492 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
493 {
494 W2BYTEMSK(REG_DVI_DTOP2_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0));
495 }
496 }
497
498 break;
499 #endif
500
501 default:
502
503 break;
504 };
505
506 _mhal_mhl_DviAutoEQSwitch(ucCbusSelect, TRUE);
507 }
508
509 //**************************************************************************
510 // [Function Name]:
511 // _mhal_mhl_Mhl24bitsModeSetting()
512 // [Description]
513 // MHL 24 bits mode setting
514 // [Arguments]:
515 //
516 // [Return]:
517 //
518 //**************************************************************************
_mhal_mhl_Mhl24bitsModeSetting(MS_U8 ucCbusSelect)519 void _mhal_mhl_Mhl24bitsModeSetting(MS_U8 ucCbusSelect)
520 {
521 switch(ucCbusSelect)
522 {
523 #if(MHL_FUNCTION_SUPPORT_PORTA)
524 case MHL_CBUS_SELECT_PORTA:
525 if(GET_MHL_PATH_SUPPORT_PORTA())
526 {
527 W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL
528 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
529 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); // auto clear phase accumulator
530 W2BYTEMSK(REG_DVI_DTOP_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
531 W2BYTEMSK(REG_DVI_DTOP_3B_L, BIT(4), BIT(4)); // overwirte enable
532 W2BYTEMSK(REG_DVI_DTOP_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
533 W2BYTEMSK(REG_DVI_DTOP_3D_L, BIT(4), BIT(4)); // overwirte enable
534 W2BYTEMSK(REG_DVI_DTOP_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
535 W2BYTEMSK(REG_DVI_DTOP_3F_L, BIT(4), BIT(4)); // overwirte enable
536 W2BYTE(REG_DVI_DTOP_30_L, (MHL_UNLOCK_RESOLUTION << 8) |MHL_LOCK_RESOLUTION);
537 W2BYTEMSK(REG_DVI_DTOP_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2));
538 W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
539 W2BYTEMSK(REG_DVI_ATOP_38_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
540 W2BYTEMSK(REG_DVI_ATOP_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
541 W2BYTEMSK(REG_HDCP_09_L, 0, BIT(0)); // PP mode + HDCP eanble
542
543 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
544 {
545 W2BYTEMSK(REG_DVI_DTOP_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0));
546 }
547 }
548
549 break;
550 #endif
551
552 #if(MHL_FUNCTION_SUPPORT_PORTB)
553 case MHL_CBUS_SELECT_PORTB:
554 if(GET_MHL_PATH_SUPPORT_PORTB())
555 {
556 W2BYTEMSK(REG_DVI_DTOP1_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL
557 W2BYTEMSK(REG_DVI_DTOP1_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
558 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); // auto clear phase accumulator
559 W2BYTEMSK(REG_DVI_DTOP1_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
560 W2BYTEMSK(REG_DVI_DTOP1_3B_L, BIT(4), BIT(4)); // overwirte enable
561 W2BYTEMSK(REG_DVI_DTOP1_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
562 W2BYTEMSK(REG_DVI_DTOP1_3D_L, BIT(4), BIT(4)); // overwirte enable
563 W2BYTEMSK(REG_DVI_DTOP1_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
564 W2BYTEMSK(REG_DVI_DTOP1_3F_L, BIT(4), BIT(4)); // overwirte enable
565 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
566 W2BYTEMSK(REG_DVI_ATOP1_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICTL value
567 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(2:1), BMASK(2:1)); // [2:0]: power down RD
568 W2BYTEMSK(REG_DVI_ATOP1_74_L, BMASK(5:0), BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power down DPLPHQ
569 W2BYTEMSK(REG_HDCP1_09_L, 0, BIT(0)); // PP mode + HDCP eanble
570
571 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
572 {
573 W2BYTEMSK(REG_DVI_DTOP1_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0));
574 }
575 }
576
577 break;
578 #endif
579
580 #if(MHL_FUNCTION_SUPPORT_PORTC)
581 case MHL_CBUS_SELECT_PORTC:
582 if(GET_MHL_PATH_SUPPORT_PORTC())
583 {
584 W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, [0]: MHL enable
585 W2BYTEMSK(REG_DVI_DTOP3_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
586 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator
587 W2BYTEMSK(REG_DVI_DTOP3_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
588 W2BYTEMSK(REG_DVI_DTOP3_3B_L, BIT(4), BIT(4)); // overwirte enable
589 W2BYTEMSK(REG_DVI_DTOP3_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
590 W2BYTEMSK(REG_DVI_DTOP3_3D_L, BIT(4), BIT(4)); // overwirte enable
591 W2BYTEMSK(REG_DVI_DTOP3_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
592 W2BYTEMSK(REG_DVI_DTOP3_3F_L, BIT(4), BIT(4)); // overwirte enable
593 W2BYTE(REG_DVI_DTOP3_30_L, (MHL_UNLOCK_RESOLUTION << 8) |MHL_LOCK_RESOLUTION);
594 W2BYTEMSK(REG_DVI_DTOP3_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2));
595 W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
596 W2BYTEMSK(REG_DVI_ATOP3_35_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
597 W2BYTEMSK(REG_DVI_ATOP3_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
598 W2BYTEMSK(REG_HDCP3_09_L, 0, BIT(0)); // PP mode + HDCP eanble
599
600 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
601 {
602 W2BYTEMSK(REG_DVI_DTOP3_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0));
603 }
604 }
605
606 break;
607 #endif
608
609 #if(MHL_FUNCTION_SUPPORT_PORTD)
610 case MHL_CBUS_SELECT_PORTD:
611 if(GET_MHL_PATH_SUPPORT_PORTD())
612 {
613 W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, [0]: MHL enable
614 W2BYTEMSK(REG_DVI_DTOP2_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
615 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); // auto clear phase accumulator
616 W2BYTEMSK(REG_DVI_DTOP2_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
617 W2BYTEMSK(REG_DVI_DTOP2_3B_L, BIT(4), BIT(4)); // overwirte enable
618 W2BYTEMSK(REG_DVI_DTOP2_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
619 W2BYTEMSK(REG_DVI_DTOP2_3D_L, BIT(4), BIT(4)); // overwirte enable
620 W2BYTEMSK(REG_DVI_DTOP2_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
621 W2BYTEMSK(REG_DVI_DTOP2_3F_L, BIT(4), BIT(4)); // overwirte enable
622 W2BYTE(REG_DVI_DTOP2_30_L, (MHL_UNLOCK_RESOLUTION << 8) |MHL_LOCK_RESOLUTION);
623 W2BYTEMSK(REG_DVI_DTOP2_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2));
624 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
625 W2BYTEMSK(REG_DVI_ATOP2_35_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
626 W2BYTEMSK(REG_DVI_ATOP2_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICTL value
627 W2BYTEMSK(REG_HDCP2_09_L, 0, BIT(0)); // PP mode + HDCP eanble
628
629 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
630 {
631 W2BYTEMSK(REG_DVI_DTOP2_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0));
632 }
633 }
634
635 break;
636 #endif
637
638 default:
639
640 break;
641 };
642
643 _mhal_mhl_DviAutoEQSwitch(ucCbusSelect, FALSE);
644 }
645
646 //**************************************************************************
647 // [Function Name]:
648 // _mhal_mhl_MhlPackedPixelModeSetting()
649 // [Description]
650 // MHL packed pixel mode setting
651 // [Arguments]:
652 //
653 // [Return]:
654 //
655 //**************************************************************************
_mhal_mhl_MhlPackedPixelModeSetting(MS_U8 ucCbusSelect)656 void _mhal_mhl_MhlPackedPixelModeSetting(MS_U8 ucCbusSelect)
657 {
658 switch(ucCbusSelect)
659 {
660 #if(MHL_FUNCTION_SUPPORT_PORTA)
661 case MHL_CBUS_SELECT_PORTA:
662 if(GET_MHL_PATH_SUPPORT_PORTA())
663 {
664 W2BYTEMSK(REG_DVI_DTOP_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL
665 W2BYTEMSK(REG_DVI_ATOP_32_L, BMASK(9:8), BMASK(9:8)); // HF
666 W2BYTEMSK(REG_HDCP_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
667 }
668
669 break;
670 #endif
671
672 #if(MHL_FUNCTION_SUPPORT_PORTB)
673 case MHL_CBUS_SELECT_PORTB:
674 if(GET_MHL_PATH_SUPPORT_PORTB())
675 {
676 W2BYTEMSK(REG_DVI_DTOP1_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL
677 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); // HF
678 W2BYTEMSK(REG_HDCP1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
679 }
680
681 break;
682 #endif
683
684 #if(MHL_FUNCTION_SUPPORT_PORTC)
685 case MHL_CBUS_SELECT_PORTC:
686 if(GET_MHL_PATH_SUPPORT_PORTC())
687 {
688 W2BYTEMSK(REG_DVI_DTOP3_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL
689 W2BYTEMSK(REG_DVI_ATOP3_32_L, BMASK(9:8), BMASK(9:8)); // HF
690 W2BYTEMSK(REG_HDCP3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
691 }
692
693 break;
694 #endif
695
696 #if(MHL_FUNCTION_SUPPORT_PORTD)
697 case MHL_CBUS_SELECT_PORTD:
698 if(GET_MHL_PATH_SUPPORT_PORTD())
699 {
700 W2BYTEMSK(REG_DVI_DTOP2_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL
701 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); // HF
702 W2BYTEMSK(REG_HDCP2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
703 }
704
705 break;
706 #endif
707
708 default:
709
710 break;
711 };
712 }
713
714 //**************************************************************************
715 // [Function Name]:
716 // _mhal_mhl_RxRtermControl()
717 // [Description]
718 // MHL TMDS termination resistor control
719 // [Arguments]:
720 //
721 // [Return]:
722 //
723 //**************************************************************************
_mhal_mhl_RxRtermControl(MS_U8 ucCbusSelect,RXRtermControl_T rctrl)724 void _mhal_mhl_RxRtermControl(MS_U8 ucCbusSelect, RXRtermControl_T rctrl)
725 {
726 switch(ucCbusSelect)
727 {
728 #if(MHL_FUNCTION_SUPPORT_PORTA)
729 case MHL_CBUS_SELECT_PORTA:
730 if(GET_MHL_PATH_SUPPORT_PORTA())
731 {
732 if (rctrl == RX_HDMI_RTERM)
733 {
734 W2BYTEMSK(REG_DVI_ATOP_60_L, 0, BMASK(13:11));// data R-term
735 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term
736 }
737 else if (rctrl == RX_MHL_RTERM)
738 {
739 W2BYTEMSK(REG_DVI_ATOP_60_L, BMASK(13:12), BMASK(13:11));// data R-term
740 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term
741 }
742 else if (rctrl == RX_RTERM_OFF)
743 {
744 W2BYTEMSK(REG_DVI_ATOP_60_L, BMASK(13:11), BMASK(13:11));// data R-term
745 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(8), BIT(8));// clock R-term
746 }
747 }
748
749 break;
750 #endif
751
752 #if(MHL_FUNCTION_SUPPORT_PORTB)
753 case MHL_CBUS_SELECT_PORTB:
754 if(GET_MHL_PATH_SUPPORT_PORTB())
755 {
756 if (rctrl == RX_HDMI_RTERM)
757 {
758 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(13:11));// data R-term
759 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term
760 }
761 else if (rctrl == RX_MHL_RTERM)
762 {
763 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:12), BMASK(13:11));// data R-term
764 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term
765 }
766 else if (rctrl == RX_RTERM_OFF)
767 {
768 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:11), BMASK(13:11));// data R-term
769 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(9), BIT(9));// clock R-term
770 }
771 }
772
773 break;
774 #endif
775
776 #if(MHL_FUNCTION_SUPPORT_PORTC)
777 case MHL_CBUS_SELECT_PORTC:
778 if(GET_MHL_PATH_SUPPORT_PORTC())
779 {
780 if (rctrl == RX_HDMI_RTERM)
781 {
782 W2BYTEMSK(REG_DVI_ATOP3_60_L, 0, BMASK(13:11));// data R-term
783 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term
784 }
785 else if (rctrl == RX_MHL_RTERM)
786 {
787 W2BYTEMSK(REG_DVI_ATOP3_60_L, BMASK(13:12), BMASK(13:11));// data R-term
788 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term
789 }
790 else if (rctrl == RX_RTERM_OFF)
791 {
792 W2BYTEMSK(REG_DVI_ATOP3_60_L, BMASK(13:11), BMASK(13:11));// data R-term
793 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(11), BIT(11));// clock R-term
794 }
795 }
796
797 break;
798 #endif
799
800 #if(MHL_FUNCTION_SUPPORT_PORTD)
801 case MHL_CBUS_SELECT_PORTD:
802 if(GET_MHL_PATH_SUPPORT_PORTD())
803 {
804 if (rctrl == RX_HDMI_RTERM)
805 {
806 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0, BMASK(13:11));// data R-term
807 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term
808 }
809 else if (rctrl == RX_MHL_RTERM)
810 {
811 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:12), BMASK(13:11));// data R-term
812 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term
813 }
814 else if (rctrl == RX_RTERM_OFF)
815 {
816 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:11), BMASK(13:11));// data R-term
817 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(10), BIT(10));// clock R-term
818 }
819 }
820
821 break;
822 #endif
823
824 default:
825
826 break;
827 };
828 }
829
830 //**************************************************************************
831 // [Function Name]:
832 // _mhal_mhl_CbusForceToStandby()
833 // [Description]
834 //
835 // [Arguments]:
836 //
837 // [Return]:
838 //
839 //**************************************************************************
_mhal_mhl_CbusForceToStandby(void)840 void _mhal_mhl_CbusForceToStandby(void)
841 {
842 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO
843 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode
844 }
845
846 //**************************************************************************
847 // [Function Name]:
848 // _mhal_mhl_MHLForceToAttach()
849 // [Description]:
850 //
851 // [Arguments]:
852 //
853 // [Return]:
854 //
855 //**************************************************************************
_mhal_mhl_MHLForceToAttach(void)856 void _mhal_mhl_MHLForceToAttach(void)
857 {
858 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14));
859 }
860
861 #if(DMHL_LG_PRADA_PATCH)
862 //**************************************************************************
863 // [Function Name]:
864 // _mhal_mhl_AdjustCommonModeResistor()
865 // [Description]:
866 //
867 // [Arguments]:
868 //
869 // [Return]:
870 //
871 //**************************************************************************
_mhal_mhl_AdjustCommonModeResistor(MS_U8 ucCbusSelect,MS_BOOL bflag)872 void _mhal_mhl_AdjustCommonModeResistor(MS_U8 ucCbusSelect, MS_BOOL bflag)
873 {
874 switch(ucCbusSelect)
875 {
876 #if(MHL_FUNCTION_SUPPORT_PORTA)
877 case MHL_CBUS_SELECT_PORTA:
878 if(GET_MHL_PATH_SUPPORT_PORTA())
879 {
880 W2BYTEMSK(REG_DVI_DTOP_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable
881 }
882
883 break;
884 #endif
885
886 #if(MHL_FUNCTION_SUPPORT_PORTB)
887 case MHL_CBUS_SELECT_PORTB:
888 if(GET_MHL_PATH_SUPPORT_PORTB())
889 {
890 W2BYTEMSK(REG_DVI_DTOP1_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable
891 }
892
893 break;
894 #endif
895
896 #if(MHL_FUNCTION_SUPPORT_PORTC)
897 case MHL_CBUS_SELECT_PORTC:
898 if(GET_MHL_PATH_SUPPORT_PORTC())
899 {
900 W2BYTEMSK(REG_DVI_DTOP3_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable
901 }
902
903 break;
904 #endif
905
906 #if(MHL_FUNCTION_SUPPORT_PORTD)
907 case MHL_CBUS_SELECT_PORTD:
908 if(GET_MHL_PATH_SUPPORT_PORTD())
909 {
910 W2BYTEMSK(REG_DVI_DTOP2_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable
911 }
912
913 break;
914 #endif
915
916 default:
917
918 break;
919 };
920 }
921
922 #endif
923
924 //**************************************************************************
925 // [Function Name]:
926 // _mhal_mhl_ClockBigChangeFlag()
927 // [Description]:
928 //
929 // [Arguments]:
930 //
931 // [Return]:
932 //
933 //**************************************************************************
_mhal_mhl_ClockBigChangeFlag(MS_U8 ucCbusSelect)934 MS_BOOL _mhal_mhl_ClockBigChangeFlag(MS_U8 ucCbusSelect)
935 {
936 MS_BOOL bindex = FALSE;
937
938 switch(ucCbusSelect)
939 {
940 #if(MHL_FUNCTION_SUPPORT_PORTA)
941 case MHL_CBUS_SELECT_PORTA:
942 if(GET_MHL_PATH_SUPPORT_PORTA())
943 {
944 bindex = ((R2BYTE(REG_DVI_ATOP_70_L) &BIT(0)) ?TRUE: FALSE);
945
946 if(bindex)
947 {
948 W2BYTEMSK(REG_DVI_ATOP_71_L, BIT(8), BIT(8));
949 W2BYTEMSK(REG_DVI_ATOP_71_L, 0, BIT(8));
950 }
951 }
952
953 break;
954 #endif
955
956 #if(MHL_FUNCTION_SUPPORT_PORTB)
957 case MHL_CBUS_SELECT_PORTB:
958 if(GET_MHL_PATH_SUPPORT_PORTB())
959 {
960 bindex = ((R2BYTE(REG_DVI_ATOP1_70_L) &BIT(0)) ?TRUE: FALSE);
961
962 if(bindex)
963 {
964 W2BYTEMSK(REG_DVI_ATOP1_71_L, BIT(8), BIT(8));
965 W2BYTEMSK(REG_DVI_ATOP1_71_L, 0, BIT(8));
966 }
967 }
968
969 break;
970 #endif
971
972 #if(MHL_FUNCTION_SUPPORT_PORTC)
973 case MHL_CBUS_SELECT_PORTC:
974 if(GET_MHL_PATH_SUPPORT_PORTC())
975 {
976 bindex = ((R2BYTE(REG_DVI_ATOP3_70_L) &BIT(0)) ?TRUE: FALSE);
977
978 if(bindex)
979 {
980 W2BYTEMSK(REG_DVI_ATOP3_71_L, BIT(8), BIT(8));
981 W2BYTEMSK(REG_DVI_ATOP3_71_L, 0, BIT(8));
982 }
983 }
984
985 break;
986 #endif
987
988 #if(MHL_FUNCTION_SUPPORT_PORTD)
989 case MHL_CBUS_SELECT_PORTD:
990 if(GET_MHL_PATH_SUPPORT_PORTD())
991 {
992 bindex = ((R2BYTE(REG_DVI_ATOP2_70_L) &BIT(0)) ?TRUE: FALSE);
993
994 if(bindex)
995 {
996 W2BYTEMSK(REG_DVI_ATOP2_71_L, BIT(8), BIT(8));
997 W2BYTEMSK(REG_DVI_ATOP2_71_L, 0, BIT(8));
998 }
999 }
1000
1001 break;
1002 #endif
1003
1004 default:
1005
1006 break;
1007 };
1008
1009 return bindex;
1010 }
1011
1012 //**************************************************************************
1013 // [Function Name]:
1014 // _mhal_mhl_CheckClockStatus()
1015 // [Description]:
1016 //
1017 // [Arguments]:
1018 //
1019 // [Return]:
1020 //
1021 //**************************************************************************
_mhal_mhl_CheckClockStatus(MS_U8 ucCbusSelect)1022 MS_U8 _mhal_mhl_CheckClockStatus(MS_U8 ucCbusSelect)
1023 {
1024 MS_BOOL bStable = FALSE;
1025 MS_U16 usClkCount = 0;
1026
1027 switch(ucCbusSelect)
1028 {
1029 #if(MHL_FUNCTION_SUPPORT_PORTA)
1030 case MHL_CBUS_SELECT_PORTA:
1031 if(GET_MHL_PATH_SUPPORT_PORTA())
1032 {
1033 usClkCount = R2BYTE(REG_DVI_DTOP_17_L) & 0x0FFF;
1034
1035 if((R2BYTE(REG_DVI_DTOP_16_L) &BIT(9)) == BIT(9))
1036 {
1037 bStable = TRUE;
1038
1039 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1040 {
1041 bStable = FALSE;
1042 }
1043 }
1044 }
1045
1046 break;
1047 #endif
1048
1049 #if(MHL_FUNCTION_SUPPORT_PORTB)
1050 case MHL_CBUS_SELECT_PORTB:
1051 if(GET_MHL_PATH_SUPPORT_PORTB())
1052 {
1053 usClkCount = R2BYTE(REG_DVI_DTOP1_17_L) & 0x0FFF;
1054
1055 if((R2BYTE(REG_DVI_DTOP1_16_L) &BIT(9)) == BIT(9))
1056 {
1057 bStable = TRUE;
1058
1059 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1060 {
1061 bStable = FALSE;
1062 }
1063 }
1064 }
1065
1066 break;
1067 #endif
1068
1069 #if(MHL_FUNCTION_SUPPORT_PORTC)
1070 case MHL_CBUS_SELECT_PORTC:
1071 if(GET_MHL_PATH_SUPPORT_PORTC())
1072 {
1073 usClkCount = R2BYTE(REG_DVI_DTOP3_17_L) & 0x0FFF;
1074
1075 if((R2BYTE(REG_DVI_DTOP3_16_L) &BIT(9)) == BIT(9))
1076 {
1077 bStable = TRUE;
1078
1079 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1080 {
1081 bStable = FALSE;
1082 }
1083 }
1084 }
1085
1086 break;
1087 #endif
1088
1089 #if(MHL_FUNCTION_SUPPORT_PORTD)
1090 case MHL_CBUS_SELECT_PORTD:
1091 if(GET_MHL_PATH_SUPPORT_PORTD())
1092 {
1093 usClkCount = R2BYTE(REG_DVI_DTOP2_17_L) & 0x0FFF;
1094
1095 if((R2BYTE(REG_DVI_DTOP2_16_L) &BIT(9)) == BIT(9))
1096 {
1097 bStable = TRUE;
1098
1099 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1100 {
1101 bStable = FALSE;
1102 }
1103 }
1104 }
1105
1106 break;
1107 #endif
1108
1109 default:
1110
1111 break;
1112 };
1113
1114 return bStable;
1115 }
1116
1117 //**************************************************************************
1118 // [Function Name]:
1119 // _mhal_mhl_RtermHWControl()
1120 // [Description]
1121 //
1122 // [Arguments]:
1123 //
1124 // [Return]:
1125 //
1126 //**************************************************************************
_mhal_mhl_RtermHWControl(MS_U8 ucCbusSelect,MS_BOOL bFlag)1127 void _mhal_mhl_RtermHWControl(MS_U8 ucCbusSelect, MS_BOOL bFlag)
1128 {
1129 switch(ucCbusSelect)
1130 {
1131 #if(MHL_FUNCTION_SUPPORT_PORTA)
1132 case MHL_CBUS_SELECT_PORTA:
1133 if(GET_MHL_PATH_SUPPORT_PORTA())
1134 {
1135 W2BYTEMSK(REG_DVI_ATOP_7F_L, bFlag ?BIT(14) :0, BIT(14));
1136 }
1137
1138 break;
1139 #endif
1140
1141 #if(MHL_FUNCTION_SUPPORT_PORTB)
1142 case MHL_CBUS_SELECT_PORTB:
1143 if(GET_MHL_PATH_SUPPORT_PORTB())
1144 {
1145
1146 }
1147
1148 break;
1149 #endif
1150
1151 #if(MHL_FUNCTION_SUPPORT_PORTC)
1152 case MHL_CBUS_SELECT_PORTC:
1153 if(GET_MHL_PATH_SUPPORT_PORTC())
1154 {
1155 W2BYTEMSK(REG_DVI_ATOP3_01_L, bFlag ?BIT(0) :0, BIT(0));
1156 }
1157
1158 break;
1159 #endif
1160
1161 #if(MHL_FUNCTION_SUPPORT_PORTD)
1162 case MHL_CBUS_SELECT_PORTD:
1163 if(GET_MHL_PATH_SUPPORT_PORTD())
1164 {
1165 W2BYTEMSK(REG_DVI_ATOP2_00_L, bFlag ?BIT(0) :0, BIT(0));
1166 }
1167
1168 break;
1169 #endif
1170
1171 default:
1172
1173 break;
1174 };
1175 }
1176
1177 //**************************************************************************
1178 // [Function Name]:
1179 // _mhal_mhl_ChangeScalerMainMux()
1180 // [Description]
1181 //
1182 // [Arguments]:
1183 //
1184 // [Return]:
1185 //
1186 //**************************************************************************
_mhal_mhl_ChangeScalerMainMux(MS_BOOL bFlag)1187 void _mhal_mhl_ChangeScalerMainMux(MS_BOOL bFlag)
1188 {
1189 MS_U8 ucScalerMainMux = (R2BYTE(0x102E02) &BMASK(7:4)) >> 4;
1190
1191 if(bFlag)
1192 {
1193 if(ucScalerMainMux == MHL_SCALER_MUX_SELECT_DVI)
1194 {
1195 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4));
1196 }
1197 }
1198 else
1199 {
1200 if(ucScalerMainMux == MHL_SCALER_MUX_SELECT_MHL)
1201 {
1202 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4));
1203 }
1204 }
1205 }
1206
1207 //**************************************************************************
1208 // [Function Name]:
1209 // _mhal_mhl_AudioPathSelect()
1210 // [Description]
1211 //
1212 // [Arguments]:
1213 //
1214 // [Return]:
1215 //
1216 //**************************************************************************
_mhal_mhl_AudioPathSelect(MS_BOOL bMHLPath)1217 void _mhal_mhl_AudioPathSelect(MS_BOOL bMHLPath)
1218 {
1219 W2BYTEMSK(REG_HDMI2_08_L, bMHLPath ?BIT(0) :0, BIT(0)); // [0]: audio source selection, 0: HDMI / 1: MHL
1220 }
1221
1222 //**************************************************************************
1223 // [Function Name]:
1224 // _mhal_mhl_CbusAndClockSelect()
1225 // [Description]
1226 //
1227 // [Arguments]:
1228 //
1229 // [Return]:
1230 //
1231 //**************************************************************************
_mhal_mhl_CbusAndClockSelect(void)1232 void _mhal_mhl_CbusAndClockSelect(void)
1233 {
1234 MS_U8 ucClockSelect = MHL_DVI_PORT_A;
1235
1236 if(GET_MHL_PATH_SUPPORT_PORTA())
1237 {
1238 ucClockSelect = MHL_DVI_PORT_A;
1239 }
1240 else if(GET_MHL_PATH_SUPPORT_PORTB())
1241 {
1242 ucClockSelect = MHL_DVI_PORT_B;
1243 }
1244 else if(GET_MHL_PATH_SUPPORT_PORTC())
1245 {
1246 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(6)| BIT(8)| BIT(0)); // [0]: reg_hplugc_mhl_en
1247 ucClockSelect = MHL_DVI_PORT_C;
1248 }
1249 else if(GET_MHL_PATH_SUPPORT_PORTD())
1250 {
1251 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(8), BIT(14)| BIT(8)| BIT(0)); // [8]: reg_hpluga_mhl_en
1252 ucClockSelect = MHL_DVI_PORT_D;
1253 }
1254
1255 W2BYTEMSK(REG_DVI_ATOP_6A_L, (ucClockSelect << 2), BMASK(3:2)); // [3:2]: HDCP clock select
1256 }
1257
1258 //**************************************************************************
1259 // [Function Name]:
1260 // _mhal_mhl_PhyInitialSetting()
1261 // [Description]
1262 //
1263 // [Arguments]:
1264 //
1265 // [Return]:
1266 //
1267 //**************************************************************************
_mhal_mhl_PhyInitialSetting(MS_U8 ucCbusSelect)1268 void _mhal_mhl_PhyInitialSetting(MS_U8 ucCbusSelect)
1269 {
1270 switch(ucCbusSelect)
1271 {
1272 #if(MHL_FUNCTION_SUPPORT_PORTA)
1273 case MHL_CBUS_SELECT_PORTA:
1274 if(GET_MHL_PATH_SUPPORT_PORTA())
1275 {
1276 W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria
1277 W2BYTEMSK(REG_DVI_DTOP_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2
1278 }
1279
1280 break;
1281 #endif
1282
1283 #if(MHL_FUNCTION_SUPPORT_PORTB)
1284 case MHL_CBUS_SELECT_PORTB:
1285 if(GET_MHL_PATH_SUPPORT_PORTB())
1286 {
1287
1288 }
1289
1290 break;
1291 #endif
1292
1293 #if(MHL_FUNCTION_SUPPORT_PORTC)
1294 case MHL_CBUS_SELECT_PORTC:
1295 if(GET_MHL_PATH_SUPPORT_PORTC())
1296 {
1297 W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria
1298 W2BYTEMSK(REG_DVI_DTOP3_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2
1299 }
1300
1301 break;
1302 #endif
1303
1304 #if(MHL_FUNCTION_SUPPORT_PORTD)
1305 case MHL_CBUS_SELECT_PORTD:
1306 if(GET_MHL_PATH_SUPPORT_PORTD())
1307 {
1308 W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria
1309 W2BYTEMSK(REG_DVI_DTOP2_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2
1310 }
1311
1312 break;
1313 #endif
1314
1315 default:
1316
1317 break;
1318 };
1319 }
1320
1321 //-------------------------------------------------------------------------------------------------
1322 // Global Functions
1323 //-------------------------------------------------------------------------------------------------
1324
1325 //**************************************************************************
1326 // [Function Name]:
1327 // mhal_mhl_GetCbusSelect()
1328 // [Description]
1329 //
1330 // [Arguments]:
1331 //
1332 // [Return]:
1333 //
1334 //**************************************************************************
mhal_mhl_GetCbusSelect(MS_U8 ucPort)1335 MS_U8 mhal_mhl_GetCbusSelect(MS_U8 ucPort)
1336 {
1337 MS_U8 uctemp = MHL_CBUS_SELECT_MASK;
1338
1339 switch(ucPort)
1340 {
1341 case MHL_DVI_PORT_A:
1342 uctemp = MHL_CBUS_SELECT_PORTA;
1343 break;
1344
1345 case MHL_DVI_PORT_B:
1346 uctemp = MHL_CBUS_SELECT_PORTB;
1347 break;
1348
1349 case MHL_DVI_PORT_C:
1350 uctemp = MHL_CBUS_SELECT_PORTC;
1351 break;
1352
1353 case MHL_DVI_PORT_D:
1354 uctemp = MHL_CBUS_SELECT_PORTD;
1355 break;
1356
1357 default:
1358
1359 break;
1360 };
1361
1362 return uctemp;
1363 }
1364
1365 //**************************************************************************
1366 // [Function Name]:
1367 // mhal_mhl_GetInputPort()
1368 // [Description]
1369 // MHL get current input port
1370 // [Arguments]:
1371 //
1372 // [Return]:
1373 //
1374 //**************************************************************************
mhal_mhl_GetInputPort(void)1375 MS_U8 mhal_mhl_GetInputPort(void)
1376 {
1377 return (R2BYTE(REG_DVI_ATOP_6A_L) &BMASK(1:0));
1378 }
1379
1380 //**************************************************************************
1381 // [Function Name]:
1382 // mhal_mhl_CheckInputPort()
1383 // [Description]
1384 // MHL check current input port
1385 // [Arguments]:
1386 //
1387 // [Return]:
1388 //
1389 //**************************************************************************
mhal_mhl_CheckInputPort(MS_U8 ucCbusSelect)1390 MS_BOOL mhal_mhl_CheckInputPort(MS_U8 ucCbusSelect)
1391 {
1392 MS_BOOL bindex = FALSE;
1393
1394 if(mhal_mhl_GetCbusSelect(mhal_mhl_GetInputPort()) == ucCbusSelect)
1395 {
1396 bindex = TRUE;
1397 }
1398
1399 return bindex;
1400 }
1401
1402 //**************************************************************************
1403 // [Function Name]:
1404 // mhal_mhl_CheckPIPWindow()
1405 // [Description]
1406 //
1407 // [Arguments]:
1408 //
1409 // [Return]:
1410 //
1411 //**************************************************************************
mhal_mhl_CheckPIPWindow(void)1412 MS_BOOL mhal_mhl_CheckPIPWindow(void)
1413 {
1414 MS_BOOL bFlag = FALSE;
1415 MS_U8 ucScalerMainMux = R2BYTE(0x102E02) &BMASK(7:0);
1416 MS_U8 ucScalerSubMux = ucScalerMainMux &BMASK(3:0);
1417
1418 ucScalerMainMux = (ucScalerMainMux &BMASK(7:4)) >> 4;
1419
1420 if((ucScalerMainMux == MHL_SCALER_MUX_SELECT_DVI) || (ucScalerMainMux == MHL_SCALER_MUX_SELECT_MHL)) // Check scaler main window mux
1421 {
1422 bFlag = TRUE;
1423 }
1424 else if((ucScalerSubMux == MHL_SCALER_MUX_SELECT_DVI) || (ucScalerSubMux == MHL_SCALER_MUX_SELECT_MHL)) // Check scaler sub window mux
1425 {
1426 bFlag = TRUE;
1427 }
1428
1429 return bFlag;
1430 }
1431
1432 //**************************************************************************
1433 // [Function Name]:
1434 // mhal_mhl_MHLSupportPath()
1435 // [Description]
1436 // MHL support path
1437 // [Arguments]:
1438 //
1439 // [Return]:
1440 //
1441 //**************************************************************************
mhal_mhl_MHLSupportPath(MS_U8 ucSelect)1442 void mhal_mhl_MHLSupportPath(MS_U8 ucSelect)
1443 {
1444 ucMHLSupportPort = ucSelect;
1445
1446 if(GET_MHL_PATH_SUPPORT_PORTC() && GET_MHL_PATH_SUPPORT_PORTD())
1447 {
1448 msg_mhl(printf("** MHL Cbus illegal support path T^T\r\n"));
1449 }
1450 }
1451
1452 //**************************************************************************
1453 // [Function Name]:
1454 // mhal_mhl_CheckEfuseControlFlag()
1455 // [Description]
1456 //
1457 // [Arguments]:
1458 //
1459 // [Return]:
1460 //
1461 //**************************************************************************
mhal_mhl_CheckEfuseControlFlag(MS_BOOL bEfuseFlag)1462 MS_BOOL mhal_mhl_CheckEfuseControlFlag(MS_BOOL bEfuseFlag)
1463 {
1464 MS_BOOL bFlag = FALSE;
1465
1466 #if(MHL_EFUSE_FUNCTION_CONTROL)
1467 MS_U8 uctemp = 0;
1468
1469 if(!bEfuseFlag)
1470 {
1471 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
1472 {
1473 mhal_mhl_CbusIsolate(uctemp, TRUE);
1474 }
1475
1476 bFlag = TRUE;
1477 }
1478
1479 #endif
1480
1481 return bFlag;
1482 }
1483
1484 //**************************************************************************
1485 // [Function Name]:
1486 // mhal_mhl_InsertChipIDforCheck()
1487 // [Description]
1488 //
1489 // [Arguments]:
1490 //
1491 // [Return]:
1492 //
1493 //**************************************************************************
mhal_mhl_InsertChipIDforCheck(MS_U8 ucChipID)1494 void mhal_mhl_InsertChipIDforCheck(MS_U8 ucChipID)
1495 {
1496 ucChipIDValue = ucChipID;
1497
1498 msg_mhl(printf("** MHL Cbus index value %x\r\n", ucChipID));
1499 }
1500
1501 //**************************************************************************
1502 // [Function Name]:
1503 // mhal_mhl_CbusSelectSetMux()
1504 // [Description]
1505 //
1506 // [Arguments]:
1507 //
1508 // [Return]:
1509 //
1510 //**************************************************************************
mhal_mhl_CbusSelectSetMux(MS_U8 ucCbusSelect)1511 void mhal_mhl_CbusSelectSetMux(MS_U8 ucCbusSelect)
1512 {
1513 switch(ucCbusSelect)
1514 {
1515 #if(MHL_FUNCTION_SUPPORT_PORTA)
1516 case MHL_CBUS_SELECT_PORTA:
1517 if(GET_MHL_PATH_SUPPORT_PORTA())
1518 {
1519
1520 }
1521
1522 break;
1523 #endif
1524
1525 #if(MHL_FUNCTION_SUPPORT_PORTB)
1526 case MHL_CBUS_SELECT_PORTB:
1527 if(GET_MHL_PATH_SUPPORT_PORTB())
1528 {
1529
1530 }
1531
1532 break;
1533 #endif
1534
1535 #if(MHL_FUNCTION_SUPPORT_PORTC)
1536 case MHL_CBUS_SELECT_PORTC:
1537 if(GET_MHL_PATH_SUPPORT_PORTC())
1538 {
1539
1540 }
1541
1542 break;
1543 #endif
1544
1545 #if(MHL_FUNCTION_SUPPORT_PORTD)
1546 case MHL_CBUS_SELECT_PORTD:
1547 if(GET_MHL_PATH_SUPPORT_PORTD())
1548 {
1549
1550 }
1551
1552 break;
1553 #endif
1554
1555 default:
1556
1557 break;
1558 };
1559 }
1560
1561 //**************************************************************************
1562 // [Function Name]:
1563 // mhal_mhl_CableDetect()
1564 // [Description]
1565 // MHL cable detection
1566 // [Arguments]:
1567 //
1568 // [Return]:
1569 // TRUE: MHL cable plugged
1570 // FALSE: MHL cable unplugged
1571 //**************************************************************************
mhal_mhl_CableDetect(MS_U8 ucCbusSelect)1572 MS_BOOL mhal_mhl_CableDetect(MS_U8 ucCbusSelect)
1573 {
1574 MS_BOOL bFlag = FALSE;
1575
1576 switch(ucCbusSelect)
1577 {
1578 #if(MHL_FUNCTION_SUPPORT_PORTA)
1579 case MHL_CBUS_SELECT_PORTA:
1580 if(GET_MHL_PATH_SUPPORT_PORTA())
1581 {
1582 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
1583 }
1584
1585 break;
1586 #endif
1587
1588 #if(MHL_FUNCTION_SUPPORT_PORTB)
1589 case MHL_CBUS_SELECT_PORTB:
1590 if(GET_MHL_PATH_SUPPORT_PORTB())
1591 {
1592
1593 }
1594
1595 break;
1596 #endif
1597
1598 #if(MHL_FUNCTION_SUPPORT_PORTC)
1599 case MHL_CBUS_SELECT_PORTC:
1600 if(GET_MHL_PATH_SUPPORT_PORTC())
1601 {
1602 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
1603 }
1604
1605 break;
1606 #endif
1607
1608 #if(MHL_FUNCTION_SUPPORT_PORTD)
1609 case MHL_CBUS_SELECT_PORTD:
1610 if(GET_MHL_PATH_SUPPORT_PORTD())
1611 {
1612 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
1613 }
1614
1615 break;
1616 #endif
1617
1618 default:
1619
1620 break;
1621 };
1622
1623 return bFlag;
1624 }
1625
1626 //**************************************************************************
1627 // [Function Name]:
1628 // mhal_mhl_Accumulator_Clr()
1629 // [Description]
1630 // to clear accumulator when input is not MHL
1631 // [Arguments]:
1632 //
1633 // [Return]:
1634 //**************************************************************************
mhal_mhl_Accumulator_Clr(MS_U8 ucCbusSelect)1635 void mhal_mhl_Accumulator_Clr(MS_U8 ucCbusSelect)
1636 {
1637 switch(ucCbusSelect)
1638 {
1639 #if(MHL_FUNCTION_SUPPORT_PORTA)
1640 case MHL_CBUS_SELECT_PORTA:
1641 if(GET_MHL_PATH_SUPPORT_PORTA())
1642 {
1643 if(R2BYTE(REG_DVI_DTOP_16_L) & BIT(9)) // clk stable
1644 {
1645 if((R2BYTE(REG_DVI_DTOP_01_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP_01_L) == 0x7FF7) ||
1646 (R2BYTE(REG_DVI_DTOP_02_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP_02_L) == 0x7FF7) ||
1647 (R2BYTE(REG_DVI_DTOP_03_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP_03_L) == 0x7FF7))
1648 {
1649 W2BYTEMSK(REG_DVI_DTOP_0E_L, BIT(4), BIT(4)); // clear accumulator
1650 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4));
1651 }
1652 }
1653 }
1654
1655 break;
1656 #endif
1657
1658 #if(MHL_FUNCTION_SUPPORT_PORTB)
1659 case MHL_CBUS_SELECT_PORTB:
1660 if(GET_MHL_PATH_SUPPORT_PORTB())
1661 {
1662 if(R2BYTE(REG_DVI_DTOP1_16_L) & BIT(9)) // clk stable
1663 {
1664 if((R2BYTE(REG_DVI_DTOP1_01_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP1_01_L) == 0x7FF7) ||
1665 (R2BYTE(REG_DVI_DTOP1_02_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP1_02_L) == 0x7FF7) ||
1666 (R2BYTE(REG_DVI_DTOP1_03_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP1_03_L) == 0x7FF7))
1667 {
1668 W2BYTEMSK(REG_DVI_DTOP1_0E_L, BIT(4), BIT(4)); // clear accumulator
1669 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4));
1670 }
1671 }
1672 }
1673
1674 break;
1675 #endif
1676
1677 #if(MHL_FUNCTION_SUPPORT_PORTC)
1678 case MHL_CBUS_SELECT_PORTC:
1679 if(GET_MHL_PATH_SUPPORT_PORTC())
1680 {
1681 if(R2BYTE(REG_DVI_DTOP3_16_L) & BIT(9)) // clk stable
1682 {
1683 if((R2BYTE(REG_DVI_DTOP3_01_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP3_01_L) == 0x7FF7) ||
1684 (R2BYTE(REG_DVI_DTOP3_02_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP3_02_L) == 0x7FF7) ||
1685 (R2BYTE(REG_DVI_DTOP3_03_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP3_03_L) == 0x7FF7))
1686 {
1687 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // clear accumulator
1688 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4));
1689 }
1690 }
1691 }
1692
1693 break;
1694 #endif
1695
1696 #if(MHL_FUNCTION_SUPPORT_PORTD)
1697 case MHL_CBUS_SELECT_PORTD:
1698 if(GET_MHL_PATH_SUPPORT_PORTD())
1699 {
1700 if(R2BYTE(REG_DVI_DTOP2_16_L) & BIT(9)) // clk stable
1701 {
1702 if((R2BYTE(REG_DVI_DTOP2_01_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP2_01_L) == 0x7FF7) ||
1703 (R2BYTE(REG_DVI_DTOP2_02_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP2_02_L) == 0x7FF7) ||
1704 (R2BYTE(REG_DVI_DTOP2_03_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP2_03_L) == 0x7FF7))
1705 {
1706 W2BYTEMSK(REG_DVI_DTOP2_0E_L, BIT(4), BIT(4)); // clear accumulator
1707 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4));
1708 }
1709 }
1710 }
1711
1712 break;
1713 #endif
1714
1715 default:
1716
1717 break;
1718 };
1719 }
1720
1721 //**************************************************************************
1722 // [Function Name]:
1723 // mhal_mhl_CDRModeMonitor()
1724 // [Description]:
1725 // MHL CDR mode monitor
1726 // [Arguments]:
1727 // isCbusConnected: Cbus is at connected state or not
1728 // [Return]:
1729 //
1730 //**************************************************************************
mhal_mhl_CDRModeMonitor(MS_U8 ucCbusSelect,MS_BOOL bPathEnable)1731 MS_BOOL mhal_mhl_CDRModeMonitor(MS_U8 ucCbusSelect, MS_BOOL bPathEnable)
1732 {
1733 MS_BOOL bindex = FALSE;
1734 static MS_U8 ucStableCount = 0;
1735 static MS_BOOL bPLLPower[MHL_CBUS_SELECT_MASK] = {TRUE, TRUE, TRUE, TRUE};
1736
1737 switch(ucCbusSelect)
1738 {
1739 #if(MHL_FUNCTION_SUPPORT_PORTA)
1740 case MHL_CBUS_SELECT_PORTA:
1741 if(GET_MHL_PATH_SUPPORT_PORTA())
1742 {
1743 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
1744 {
1745 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
1746 {
1747 ucStableCount++;
1748 }
1749
1750 if((R2BYTE(REG_DVI_DTOP_31_L) &BIT(6)) == BIT(6)) // DE stable
1751 {
1752 if(!bPLLPower[ucCbusSelect])
1753 {
1754 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12));
1755 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12));
1756
1757 bPLLPower[ucCbusSelect] = TRUE;
1758 }
1759 }
1760 else // DE unstable
1761 {
1762 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
1763 {
1764 ucStableCount = 0;
1765 bPLLPower[ucCbusSelect] = FALSE;
1766 }
1767 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -MHL_CDR_STABLE_OFFSET))
1768 {
1769 bPLLPower[ucCbusSelect] = TRUE;
1770 }
1771 }
1772 }
1773 else
1774 {
1775 if(bPLLPower[ucCbusSelect])
1776 {
1777 bPLLPower[ucCbusSelect] = FALSE;
1778 ucStableCount = 0;
1779 }
1780 }
1781 }
1782
1783 break;
1784 #endif
1785
1786 #if(MHL_FUNCTION_SUPPORT_PORTB)
1787 case MHL_CBUS_SELECT_PORTB:
1788 if(GET_MHL_PATH_SUPPORT_PORTB())
1789 {
1790
1791 }
1792
1793 break;
1794 #endif
1795
1796 #if(MHL_FUNCTION_SUPPORT_PORTC)
1797 case MHL_CBUS_SELECT_PORTC:
1798 if(GET_MHL_PATH_SUPPORT_PORTC())
1799 {
1800 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
1801 {
1802 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
1803 {
1804 ucStableCount++;
1805 }
1806
1807 if((R2BYTE(REG_DVI_DTOP3_31_L) &BIT(6)) == BIT(6)) // DE stable
1808 {
1809 if(!bPLLPower[ucCbusSelect])
1810 {
1811 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12));
1812 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12));
1813
1814 bPLLPower[ucCbusSelect] = TRUE;
1815 }
1816 }
1817 else // DE unstable
1818 {
1819 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
1820 {
1821 ucStableCount = 0;
1822 bPLLPower[ucCbusSelect] = FALSE;
1823 }
1824 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -MHL_CDR_STABLE_OFFSET))
1825 {
1826 bPLLPower[ucCbusSelect] = TRUE;
1827 }
1828 }
1829 }
1830 else
1831 {
1832 if(bPLLPower[ucCbusSelect])
1833 {
1834 bPLLPower[ucCbusSelect] = FALSE;
1835 ucStableCount = 0;
1836 }
1837 }
1838 }
1839
1840 break;
1841 #endif
1842
1843 #if(MHL_FUNCTION_SUPPORT_PORTD)
1844 case MHL_CBUS_SELECT_PORTD:
1845 if(GET_MHL_PATH_SUPPORT_PORTD())
1846 {
1847 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
1848 {
1849 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
1850 {
1851 ucStableCount++;
1852 }
1853
1854 if((R2BYTE(REG_DVI_DTOP2_31_L) &BIT(6)) == BIT(6)) // DE stable
1855 {
1856 if(!bPLLPower[ucCbusSelect])
1857 {
1858 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12));
1859 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12));
1860
1861 bPLLPower[ucCbusSelect] = TRUE;
1862 }
1863 }
1864 else // DE unstable
1865 {
1866 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
1867 {
1868 ucStableCount = 0;
1869 bPLLPower[ucCbusSelect] = FALSE;
1870 }
1871 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -MHL_CDR_STABLE_OFFSET))
1872 {
1873 bPLLPower[ucCbusSelect] = TRUE;
1874 }
1875 }
1876 }
1877 else
1878 {
1879 if(bPLLPower[ucCbusSelect])
1880 {
1881 bPLLPower[ucCbusSelect] = FALSE;
1882 ucStableCount = 0;
1883 }
1884 }
1885 }
1886
1887 break;
1888 #endif
1889
1890 default:
1891
1892 break;
1893 };
1894
1895 if(ucStableCount >= MHL_CDR_FORCE_THRESHOLD)
1896 {
1897 bMHLSignalStable = TRUE;
1898 }
1899 else if(bMHLSignalStable)
1900 {
1901 bMHLSignalStable = FALSE;
1902 }
1903
1904 return bindex;
1905 }
1906
1907 //**************************************************************************
1908 // [Function Name]:
1909 // mhal_mhl_CbusIsolate()
1910 // [Description]
1911 // MHL cable isolate
1912 // [Arguments]:
1913 //
1914 // [Return]:
1915 //
1916 //**************************************************************************
mhal_mhl_CbusIsolate(MS_U8 ucCbusSelect,MS_BOOL bFlag)1917 void mhal_mhl_CbusIsolate(MS_U8 ucCbusSelect, MS_BOOL bFlag)
1918 {
1919 switch(ucCbusSelect)
1920 {
1921 #if(MHL_FUNCTION_SUPPORT_PORTA)
1922 case MHL_CBUS_SELECT_PORTA:
1923 if(GET_MHL_PATH_SUPPORT_PORTA())
1924 {
1925 if(bFlag)
1926 {
1927 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
1928 }
1929 else
1930 {
1931 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
1932 }
1933 }
1934
1935 break;
1936 #endif
1937
1938 #if(MHL_FUNCTION_SUPPORT_PORTB)
1939 case MHL_CBUS_SELECT_PORTB:
1940 if(GET_MHL_PATH_SUPPORT_PORTB())
1941 {
1942
1943 }
1944
1945 break;
1946 #endif
1947
1948 #if(MHL_FUNCTION_SUPPORT_PORTC)
1949 case MHL_CBUS_SELECT_PORTC:
1950 if(GET_MHL_PATH_SUPPORT_PORTC())
1951 {
1952 if(bFlag)
1953 {
1954 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
1955 }
1956 else
1957 {
1958 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
1959 }
1960 }
1961
1962 break;
1963 #endif
1964
1965 #if(MHL_FUNCTION_SUPPORT_PORTD)
1966 case MHL_CBUS_SELECT_PORTD:
1967 if(GET_MHL_PATH_SUPPORT_PORTD())
1968 {
1969 if(bFlag)
1970 {
1971 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
1972 }
1973 else
1974 {
1975 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
1976 }
1977 }
1978
1979 break;
1980 #endif
1981
1982 default:
1983
1984 break;
1985 };
1986 }
1987
1988 //**************************************************************************
1989 // [Function Name]:
1990 // mhal_mhl_VbusCharge()
1991 // [Description]
1992 // MHL Vbus charge
1993 // [Arguments]:
1994 //
1995 // [Return]:
1996 //
1997 //**************************************************************************
mhal_mhl_VbusCharge(MS_U8 ucCbusSelect,MS_U8 bState)1998 void mhal_mhl_VbusCharge(MS_U8 ucCbusSelect, MS_U8 bState)
1999 {
2000 switch(ucCbusSelect)
2001 {
2002 #if(MHL_FUNCTION_SUPPORT_PORTA)
2003 case MHL_CBUS_SELECT_PORTA:
2004 if(GET_MHL_PATH_SUPPORT_PORTA())
2005 {
2006 if(bState == VBUS_SW_CHARGE)
2007 {
2008 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2009 }
2010 else if(bState == VBUS_SW_UNCHARGE)
2011 {
2012 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2013 }
2014 else
2015 {
2016 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2017 }
2018 }
2019
2020 break;
2021 #endif
2022
2023 #if(MHL_FUNCTION_SUPPORT_PORTB)
2024 case MHL_CBUS_SELECT_PORTB:
2025 if(GET_MHL_PATH_SUPPORT_PORTB())
2026 {
2027
2028 }
2029
2030 break;
2031 #endif
2032
2033 #if(MHL_FUNCTION_SUPPORT_PORTC)
2034 case MHL_CBUS_SELECT_PORTC:
2035 if(GET_MHL_PATH_SUPPORT_PORTC())
2036 {
2037 if(bState == VBUS_SW_CHARGE)
2038 {
2039 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2040 }
2041 else if(bState == VBUS_SW_UNCHARGE)
2042 {
2043 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2044 }
2045 else
2046 {
2047 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2048 }
2049 }
2050
2051 break;
2052 #endif
2053
2054 #if(MHL_FUNCTION_SUPPORT_PORTD)
2055 case MHL_CBUS_SELECT_PORTD:
2056 if(GET_MHL_PATH_SUPPORT_PORTD())
2057 {
2058 if(bState == VBUS_SW_CHARGE)
2059 {
2060 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2061 }
2062 else if(bState == VBUS_SW_UNCHARGE)
2063 {
2064 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2065 }
2066 else
2067 {
2068 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2069 }
2070 }
2071
2072 break;
2073 #endif
2074
2075 default:
2076
2077 break;
2078 };
2079 }
2080
2081 //**************************************************************************
2082 // [Function Name]:
2083 // mhal_mhl_CbusFloating()
2084 // [Description]
2085 // MHL cable floating
2086 // [Arguments]:
2087 //
2088 // [Return]:
2089 //
2090 //**************************************************************************
mhal_mhl_CbusFloating(MS_BOOL bFlag)2091 void mhal_mhl_CbusFloating(MS_BOOL bFlag)
2092 {
2093 if(bFlag)
2094 {
2095 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5));
2096 }
2097 else
2098 {
2099 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5));
2100 }
2101 }
2102
2103 //**************************************************************************
2104 // [Function Name]:
2105 // mhal_mhl_CbusStucktoLow()
2106 // [Description]
2107 //
2108 // [Arguments]:
2109 //
2110 // [Return]:
2111 //
2112 //**************************************************************************
mhal_mhl_CbusStucktoLow(MS_BOOL bFlag)2113 void mhal_mhl_CbusStucktoLow(MS_BOOL bFlag)
2114 {
2115 if(bFlag)
2116 {
2117 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask
2118 }
2119 else
2120 {
2121 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask
2122 }
2123
2124 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag
2125 }
2126
2127 //**************************************************************************
2128 // [Function Name]:
2129 // mhal_mhl_CbusWakeupInterrupt()
2130 // [Description]
2131 //
2132 // [Arguments]:
2133 //
2134 // [Return]:
2135 //
2136 //**************************************************************************
mhal_mhl_CbusWakeupInterrupt(MS_BOOL bFlag)2137 void mhal_mhl_CbusWakeupInterrupt(MS_BOOL bFlag)
2138 {
2139 if(bFlag)
2140 {
2141 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask
2142 }
2143 else
2144 {
2145 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask
2146 }
2147
2148 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag
2149 }
2150
2151 //**************************************************************************
2152 // [Function Name]:
2153 // mhal_mhl_SetVenderID()
2154 // [Description]
2155 //
2156 // [Arguments]:
2157 //
2158 // [Return]:
2159 //
2160 //**************************************************************************
mhal_mhl_SetVenderID(MS_U8 ucVenderID)2161 void mhal_mhl_SetVenderID(MS_U8 ucVenderID)
2162 {
2163 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8));
2164 }
2165
2166 //**************************************************************************
2167 // [Function Name]:
2168 // mhal_mhl_LoadEDID()
2169 // [Description]
2170 //
2171 // [Arguments]:
2172 //
2173 // [Return]:
2174 //
2175 //**************************************************************************
mhal_mhl_LoadEDID(MS_U8 * edid)2176 void mhal_mhl_LoadEDID(MS_U8 *edid)
2177 {
2178 MS_U16 ustemp = 0;
2179
2180 if(edid != NULL)
2181 {
2182 // Load EDID
2183 msg_mhl(printf("** Mustang Load MHL EDID...\r\n"));
2184
2185 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable
2186
2187 for(ustemp = 0; ustemp <256; ustemp++)
2188 {
2189 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address
2190 W2BYTEMSK(REG_MHL_CBUS_53, edid[ustemp], 0x00FF); // data
2191 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger
2192 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0));
2193 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5));
2194 }
2195
2196 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable
2197 }
2198 }
2199
2200 //**************************************************************************
2201 // [Function Name]:
2202 // mhal_mhl_ReadEDID()
2203 // [Description]
2204 //
2205 // [Arguments]:
2206 //
2207 // [Return]:
2208 //
2209 //**************************************************************************
mhal_mhl_ReadEDID(MS_U16 usSize,MS_U8 * edid)2210 void mhal_mhl_ReadEDID(MS_U16 usSize, MS_U8 *edid)
2211 {
2212 MS_U16 ustemp = 0;
2213
2214 if(edid != NULL)
2215 {
2216 // Read EDID
2217 msg_mhl(printf("** Mustang Read MHL EDID...\r\n"));
2218
2219 for(ustemp = 0; ustemp < usSize; ustemp++)
2220 {
2221 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address
2222 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger
2223 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0));
2224 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4));
2225
2226 edid[ustemp] = (MS_U8)((R2BYTE(REG_MHL_CBUS_53) & 0xFF00) >> 8); // data
2227 }
2228 }
2229 }
2230
2231 //**************************************************************************
2232 // [Function Name]:
2233 // mhal_mhl_LoadDeviceCapability()
2234 // [Description]
2235 //
2236 // [Arguments]:
2237 //
2238 // [Return]:
2239 //
2240 //**************************************************************************
mhal_mhl_LoadDeviceCapability(MS_U8 * devcap)2241 void mhal_mhl_LoadDeviceCapability(MS_U8 *devcap)
2242 {
2243 MS_U8 ucIndex = 0;
2244 MS_U8 uctemp = 0;
2245
2246 if(devcap != NULL)
2247 {
2248 msg_mhl(printf("** Mustang Load DevCap...\r\n"));
2249
2250 // Load MHL device capability
2251 for(uctemp = 0; uctemp <8; uctemp++)
2252 {
2253 if(uctemp == 2)
2254 {
2255 ucIndex = 1;
2256 }
2257
2258 W2BYTE(REG_MHL_CBUS_01 +(uctemp *2), (devcap[(uctemp *2) +1 -ucIndex] <<8) | devcap[uctemp *2 -ucIndex]);
2259 }
2260
2261 W2BYTE(REG_MHL_CBUS_03, (devcap[3] <<8) | devcap[4]);
2262 W2BYTE(REG_MHL_CBUS_07, (devcap[11] <<8) | devcap[12]);
2263
2264 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0));
2265 }
2266 }
2267
2268 //**************************************************************************
2269 // [Function Name]:
2270 // mhal_mhl_initial()
2271 // [Description]
2272 // MHL init
2273 // [Arguments]:
2274 // *edid: MHL EDID data
2275 // *devcap: MHL device capability
2276 // [Return]:
2277 //
2278 //**************************************************************************
mhal_mhl_initial(MS_U8 * edid,MS_U8 * devcap,MS_U8 ucVenderID)2279 MS_U8 mhal_mhl_initial(MS_U8 *edid, MS_U8 *devcap, MS_U8 ucVenderID)
2280 {
2281 MS_U16 uctemp = 0;
2282
2283 // Initial setting
2284 for(uctemp = 0; uctemp <(sizeof(tMHL_INITIAL_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
2285 {
2286 W2BYTEMSK(tMHL_INITIAL_TABLE[uctemp].addr, tMHL_INITIAL_TABLE[uctemp].databuf, tMHL_INITIAL_TABLE[uctemp].mask);
2287 }
2288
2289 if(ucMHLSupportPort != E_MUX_NOT_SUPPORT_MHL)
2290 {
2291 W2BYTEMSK(REG_PM_SLEEP_72_L, BIT(6), BIT(6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en_sel , [6]: reg_mhl_cable_detect_sel
2292 }
2293
2294 _mhal_mhl_CbusAndClockSelect();
2295
2296 #if(MHL_INTERRUPT_USE_PM_IRQ)
2297 // Open PM irq mask
2298 W2BYTEMSK(0x2B28, 0, BIT(11));
2299 #endif
2300
2301 // Load EDID
2302 mhal_mhl_LoadEDID(edid);
2303
2304 // Load vendor ID
2305 mhal_mhl_SetVenderID(ucVenderID);
2306
2307 // Load DevCap
2308 mhal_mhl_LoadDeviceCapability(devcap);
2309
2310 // Clear Cbus received interrupt status
2311 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask
2312
2313 mhal_mhl_CbusStucktoLow(FALSE);
2314 mhal_mhl_CbusWakeupInterrupt(FALSE);
2315
2316 _mhal_mhl_MHLForceToAttach();
2317
2318 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
2319 {
2320 _mhal_mhl_RtermHWControl(uctemp, FALSE);
2321 _mhal_mhl_PhyInitialSetting(uctemp);
2322 }
2323
2324 #if(DMHL_TEST_SIGNAL_SUPPORT)
2325 W2BYTEMSK(0x001102, BIT(7), BIT(7));
2326 W2BYTEMSK(0x001128, BIT(0), BIT(0));
2327
2328 #endif
2329
2330 mhal_mhl_CbusFloating(TRUE);
2331
2332 return MHL_CHIP_FUNCTION_CAPABILITY;
2333 }
2334
2335 //**************************************************************************
2336 // [Function Name]:
2337 // mhal_mhl_InvertCableDetect()
2338 // [Description]
2339 //
2340 // [Arguments]:
2341 //
2342 // [Return]:
2343 //
2344 //**************************************************************************
mhal_mhl_InvertCableDetect(MS_U8 ucCbusSelect,MS_BOOL bCableDetectInvert)2345 void mhal_mhl_InvertCableDetect(MS_U8 ucCbusSelect, MS_BOOL bCableDetectInvert)
2346 {
2347 switch(ucCbusSelect)
2348 {
2349 #if(MHL_FUNCTION_SUPPORT_PORTA)
2350 case MHL_CBUS_SELECT_PORTA:
2351 if(GET_MHL_PATH_SUPPORT_PORTA())
2352 {
2353 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
2354 }
2355
2356 break;
2357 #endif
2358
2359 #if(MHL_FUNCTION_SUPPORT_PORTB)
2360 case MHL_CBUS_SELECT_PORTB:
2361 if(GET_MHL_PATH_SUPPORT_PORTB())
2362 {
2363
2364 }
2365
2366 break;
2367 #endif
2368
2369 #if(MHL_FUNCTION_SUPPORT_PORTC)
2370 case MHL_CBUS_SELECT_PORTC:
2371 if(GET_MHL_PATH_SUPPORT_PORTC())
2372 {
2373 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
2374 }
2375
2376 break;
2377 #endif
2378
2379 #if(MHL_FUNCTION_SUPPORT_PORTD)
2380 case MHL_CBUS_SELECT_PORTD:
2381 if(GET_MHL_PATH_SUPPORT_PORTD())
2382 {
2383 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
2384 }
2385
2386 break;
2387 #endif
2388
2389 default:
2390
2391 break;
2392 };
2393 }
2394
2395 //**************************************************************************
2396 // [Function Name]:
2397 // mhal_mhl_VbusConfigSetting()
2398 // [Description]
2399 //
2400 // [Arguments]:
2401 //
2402 // [Return]:
2403 //
2404 //**************************************************************************
mhal_mhl_VbusConfigSetting(MS_U8 ucCbusSelect,MS_U8 ucState)2405 void mhal_mhl_VbusConfigSetting(MS_U8 ucCbusSelect, MS_U8 ucState)
2406 {
2407 MS_U8 ucOutputState = ucState &(MHL_VBUS_LOW_ENABLE_MODE | MHL_VBUS_HIGH_ENABLE_MODE);
2408
2409 ucState = ucState &(MHL_VBUS_OUTPUT_MODE | MHL_VBUS_INVERSE_MODE);
2410
2411 switch(ucCbusSelect)
2412 {
2413 #if(MHL_FUNCTION_SUPPORT_PORTA)
2414 case MHL_CBUS_SELECT_PORTA:
2415 if(GET_MHL_PATH_SUPPORT_PORTA())
2416 {
2417 if(ucState == MHL_VBUS_OUTPUT_MODE)
2418 {
2419 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2420 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
2421 }
2422 else if(ucState > 0)
2423 {
2424 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2425 }
2426
2427 if(ucOutputState > 0)
2428 {
2429 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
2430 {
2431 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
2432 }
2433 else
2434 {
2435 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
2436 }
2437 }
2438 }
2439
2440 break;
2441 #endif
2442
2443 #if(MHL_FUNCTION_SUPPORT_PORTB)
2444 case MHL_CBUS_SELECT_PORTB:
2445 if(GET_MHL_PATH_SUPPORT_PORTB())
2446 {
2447
2448 }
2449
2450 break;
2451 #endif
2452
2453 #if(MHL_FUNCTION_SUPPORT_PORTC)
2454 case MHL_CBUS_SELECT_PORTC:
2455 if(GET_MHL_PATH_SUPPORT_PORTC())
2456 {
2457 if(ucState == MHL_VBUS_OUTPUT_MODE)
2458 {
2459 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2460 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
2461 }
2462 else if(ucState > 0)
2463 {
2464 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2465 }
2466
2467 if(ucOutputState > 0)
2468 {
2469 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
2470 {
2471 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
2472 }
2473 else
2474 {
2475 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
2476 }
2477 }
2478 }
2479
2480 break;
2481 #endif
2482
2483 #if(MHL_FUNCTION_SUPPORT_PORTD)
2484 case MHL_CBUS_SELECT_PORTD:
2485 if(GET_MHL_PATH_SUPPORT_PORTD())
2486 {
2487 if(ucState == MHL_VBUS_OUTPUT_MODE)
2488 {
2489 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2490 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
2491 }
2492 else if(ucState > 0)
2493 {
2494 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2495 }
2496
2497 if(ucOutputState > 0)
2498 {
2499 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
2500 {
2501 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
2502 }
2503 else
2504 {
2505 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
2506 }
2507 }
2508 }
2509
2510 break;
2511 #endif
2512
2513 default:
2514
2515 break;
2516 };
2517 }
2518
2519 //**************************************************************************
2520 // [Function Name]:
2521 // mhal_mhl_CableDetectPadSetting()
2522 // [Description]
2523 //
2524 // [Arguments]:
2525 //
2526 // [Return]:
2527 //
2528 //**************************************************************************
mhal_mhl_CableDetectPadSetting(MS_U8 ucSelect)2529 void mhal_mhl_CableDetectPadSetting(MS_U8 ucSelect)
2530 {
2531 if((ucSelect &MHL_CABLE_DETECT_SELECT_PORTC) && (ucSelect &MHL_CABLE_DETECT_SELECT_PORTD))
2532 {
2533 msg_mhl(printf("** MHL cable detect only select one port T^T\r\n"));
2534 }
2535 else
2536 {
2537 // Do nothing
2538 }
2539 }
2540
2541 //**************************************************************************
2542 // [Function Name]:
2543 // mhal_mhl_CbusPadConfigSwitch()
2544 // [Description]
2545 //
2546 // [Arguments]:
2547 //
2548 // [Return]:
2549 //
2550 //**************************************************************************
mhal_mhl_CbusPadConfigSwitch(MS_U8 ucCbusSelect,MS_BOOL bFlag)2551 void mhal_mhl_CbusPadConfigSwitch(MS_U8 ucCbusSelect, MS_BOOL bFlag)
2552 {
2553 switch(ucCbusSelect)
2554 {
2555 #if(MHL_FUNCTION_SUPPORT_PORTA)
2556 case MHL_CBUS_SELECT_PORTA:
2557 if(GET_MHL_PATH_SUPPORT_PORTA())
2558 {
2559 if(bFlag)
2560 {
2561 _mhal_mhl_MHLForceToAttach();
2562 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
2563 }
2564 else
2565 {
2566 _mhal_mhl_CbusForceToStandby();
2567 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
2568 }
2569 }
2570
2571 break;
2572 #endif
2573
2574 #if(MHL_FUNCTION_SUPPORT_PORTB)
2575 case MHL_CBUS_SELECT_PORTB:
2576 if(GET_MHL_PATH_SUPPORT_PORTB())
2577 {
2578
2579 }
2580
2581 break;
2582 #endif
2583
2584 #if(MHL_FUNCTION_SUPPORT_PORTC)
2585 case MHL_CBUS_SELECT_PORTC:
2586 if(GET_MHL_PATH_SUPPORT_PORTC())
2587 {
2588 if(bFlag)
2589 {
2590 _mhal_mhl_MHLForceToAttach();
2591 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
2592 }
2593 else
2594 {
2595 _mhal_mhl_CbusForceToStandby();
2596 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
2597 }
2598 }
2599
2600 break;
2601 #endif
2602
2603 #if(MHL_FUNCTION_SUPPORT_PORTD)
2604 case MHL_CBUS_SELECT_PORTD:
2605 if(GET_MHL_PATH_SUPPORT_PORTD())
2606 {
2607 if(bFlag)
2608 {
2609 _mhal_mhl_MHLForceToAttach();
2610 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
2611 }
2612 else
2613 {
2614 _mhal_mhl_CbusForceToStandby();
2615 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
2616 }
2617 }
2618
2619 break;
2620 #endif
2621
2622 default:
2623
2624 break;
2625 };
2626 }
2627
2628 //**************************************************************************
2629 // [Function Name]:
2630 // _mhal_mhl_CbusStatus()
2631 // [Description]:
2632 // MHL Cbus status
2633 // [Arguments]:
2634 //
2635 // [Return]:
2636 // Cbus status value
2637 //**************************************************************************
mhal_mhl_CbusStatus(void)2638 MS_U16 mhal_mhl_CbusStatus(void)
2639 {
2640 return (R2BYTE(REG_PM_MHL_CBUS_17));
2641 }
2642
2643 //**************************************************************************
2644 // [Function Name]:
2645 // mhal_mhl_CbusIsMscMsgReceived()
2646 // [Description]
2647 // MHL Cbus check whether msc message is received or not
2648 // [Arguments]:
2649 //
2650 // [Return]:
2651 // TRUE: recieved
2652 // FALSE: not yet
2653 //**************************************************************************
mhal_mhl_CbusIsMscMsgReceived(void)2654 MS_BOOL mhal_mhl_CbusIsMscMsgReceived(void)
2655 {
2656 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE);
2657
2658 if(bindex)
2659 {
2660 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0));
2661 }
2662
2663 return bindex;
2664 }
2665
2666 //**************************************************************************
2667 // [Function Name]:
2668 // mhal_mhl_CbusStucktoLowFlag()
2669 // [Description]
2670 //
2671 // [Arguments]:
2672 //
2673 // [Return]:
2674 //
2675 //**************************************************************************
mhal_mhl_CbusStucktoLowFlag(void)2676 MS_BOOL mhal_mhl_CbusStucktoLowFlag(void)
2677 {
2678 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(3)) ?TRUE: FALSE);
2679
2680 if(bindex)
2681 {
2682 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0));
2683 }
2684
2685 return bindex;
2686 }
2687
2688 //**************************************************************************
2689 // [Function Name]:
2690 // mhal_mhl_CbusWakeupIntFlag()
2691 // [Description]
2692 //
2693 // [Arguments]:
2694 //
2695 // [Return]:
2696 //
2697 //**************************************************************************
mhal_mhl_CbusWakeupIntFlag(void)2698 MS_BOOL mhal_mhl_CbusWakeupIntFlag(void)
2699 {
2700 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(7)) ?TRUE: FALSE);
2701
2702 if(bindex)
2703 {
2704 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4));
2705 }
2706
2707 return bindex;
2708 }
2709
2710 //**************************************************************************
2711 // [Function Name]:
2712 // mhal_mhl_CBusWrite()
2713 // [Description]
2714 // MHL Cbus write trigger
2715 // [Arguments]:
2716 // *pdatabuf: Cbus tx data
2717 // [Return]:
2718 //
2719 //**************************************************************************
mhal_mhl_CBusWrite(mhalCbusFifo_S * pdatabuf)2720 MS_BOOL mhal_mhl_CBusWrite(mhalCbusFifo_S *pdatabuf)
2721 {
2722 MS_U8 uctemp = 0;
2723
2724 if(_mhal_mhl_IsCbusBusy())
2725 {
2726 return FALSE;
2727 }
2728
2729 for(uctemp = 0; uctemp < pdatabuf->lens; uctemp++)
2730 {
2731 W2BYTE(REG_MHL_CBUS_26 +uctemp *2, pdatabuf->databuf[uctemp]);
2732 }
2733
2734 // clear the unsed parts
2735 W2BYTE(REG_MHL_CBUS_26 +((pdatabuf->lens) *2), 0);
2736
2737 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send
2738
2739 return TRUE;
2740 }
2741
2742 //**************************************************************************
2743 // [Function Name]:
2744 // _mhal_mhl_Cbus_SetPathEn()
2745 // [Description]:
2746 // MHL Cbus set path enable
2747 // [Arguments]:
2748 // TRUE: Enable
2749 // FALSE: Disable
2750 // [Return]:
2751 //
2752 //**************************************************************************
mhal_mhl_Cbus_SetPathEn(MS_BOOL bflag)2753 void mhal_mhl_Cbus_SetPathEn(MS_BOOL bflag)
2754 {
2755 if(bflag) // set state to PATH_EN
2756 {
2757 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12));
2758 }
2759 else // clear state to not PATH_EN
2760 {
2761 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13));
2762 }
2763 }
2764
2765 //**************************************************************************
2766 // [Function Name]:
2767 // mhal_mhl_CbusIntCB()
2768 // [Description]
2769 // MHL Cbus Interrupt Call Back function
2770 // [Arguments]:
2771 // *rcstate: recevied state, 0:normal / 1:timeout
2772 // *rccmd: recevied command
2773 // *rcdata: recevied data
2774 // *rclen: received length
2775 // *bIsCmdInData: Is command in data field
2776 // [Return]:
2777 //
2778 //**************************************************************************
mhal_mhl_CbusIntCB(MS_U8 * rcstate,MS_U8 * rccmd,MS_U8 * rcdata,MS_U8 * rclen,MS_U8 * bIsCmdInData)2779 MS_BOOL mhal_mhl_CbusIntCB(MS_U8 *rcstate, MS_U8 *rccmd, MS_U8 *rcdata, MS_U8 *rclen, MS_U8 *bIsCmdInData)
2780 {
2781 MS_BOOL bindex = FALSE;
2782 MS_U8 uctemp = 0;
2783 MS_U16 reg_val;
2784
2785 *rcstate = R2BYTE(REG_MHL_CBUS_3B) & 0x000F; // received state, 0: normal, 1: timeout
2786
2787 //W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); // clear INT
2788
2789 reg_val = R2BYTE(REG_MHL_CBUS_3C);
2790
2791 if(!(reg_val &BIT(8))) // Received data
2792 {
2793 bindex = TRUE;
2794 }
2795
2796 *rccmd = reg_val & 0x00FF;
2797 *bIsCmdInData = FALSE;
2798
2799 for(uctemp = 0; uctemp <=(MHL_CBUS_DATA_SIZE +1); uctemp++) // offset+16bytes+EOF
2800 {
2801 reg_val = R2BYTE(REG_MHL_CBUS_3D +(uctemp *2));
2802
2803 if(reg_val & BIT(15))
2804 {
2805 rcdata[uctemp] = reg_val & 0x00FF;
2806
2807 if(((uctemp <= 2) ||(uctemp == (MHL_CBUS_DATA_SIZE +1))) && !(*bIsCmdInData))
2808 {
2809 *bIsCmdInData = (reg_val & BIT(8)) ? TRUE : FALSE;
2810 }
2811 }
2812 else
2813 {
2814 *rclen = uctemp;
2815 break;
2816 }
2817 }
2818
2819 // CTS 6.3.11.19
2820 if(uctemp >(MHL_CBUS_DATA_SIZE +1))
2821 {
2822 *rclen = MHL_CBUS_DATA_SIZE +2;
2823 }
2824
2825 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO
2826
2827 return bindex;
2828 }
2829
2830 //**************************************************************************
2831 // [Function Name]:
2832 // mdrv_mhl_CBusCheckBCHError()
2833 // [Description]:
2834 // MHL Cbus check BCH error
2835 // [Arguments]:
2836 //
2837 // [Return]:
2838 //
2839 //**************************************************************************
mhal_mhl_CBusCheckBCHError(void)2840 MS_BOOL mhal_mhl_CBusCheckBCHError(void)
2841 {
2842 MS_BOOL bindex = FALSE;
2843
2844 if(R2BYTE(REG_HDMI_04_L) &BIT(1))
2845 {
2846 //bindex = TRUE;
2847
2848 W2BYTEMSK(REG_HDMI_04_L, BIT(1), BIT(1));
2849 }
2850
2851 return bindex;
2852 }
2853
2854 //**************************************************************************
2855 // [Function Name]:
2856 // mhal_mhl_CablePlugProc()
2857 // [Description]
2858 //
2859 // [Arguments]:
2860 //
2861 // [Return]:
2862 //
2863 //**************************************************************************
mhal_mhl_CablePlugProc(MS_U8 ucCbusSelect)2864 void mhal_mhl_CablePlugProc(MS_U8 ucCbusSelect)
2865 {
2866 _mhal_mhl_Mhl24bitsModeSetting(ucCbusSelect);
2867
2868 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
2869
2870 #if(DMHL_LG_PRADA_PATCH)
2871 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
2872 #endif
2873
2874 if(mhal_mhl_CheckInputPort(ucCbusSelect))
2875 {
2876 //_mhal_mhl_ChangeScalerMainMux(TRUE);
2877 //_mhal_mhl_AudioPathSelect(TRUE);
2878 }
2879 }
2880
2881 //**************************************************************************
2882 // [Function Name]:
2883 // mhal_mhl_CableRemoveProc()
2884 // [Description]
2885 //
2886 // [Arguments]:
2887 //
2888 // [Return]:
2889 //
2890 //**************************************************************************
mhal_mhl_CableRemoveProc(MS_U8 ucCbusSelect)2891 void mhal_mhl_CableRemoveProc(MS_U8 ucCbusSelect)
2892 {
2893 _mhal_mhl_HdmiBypassModeSetting(ucCbusSelect);
2894 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_HDMI_RTERM);
2895
2896 if(mhal_mhl_CheckInputPort(ucCbusSelect))
2897 {
2898 //_mhal_mhl_ChangeScalerMainMux(FALSE);
2899 //_mhal_mhl_AudioPathSelect(FALSE);
2900 }
2901 }
2902
2903 //**************************************************************************
2904 // [Function Name]:
2905 // mhal_mhl_CbusConnectProc()
2906 // [Description]
2907 //
2908 // [Arguments]:
2909 //
2910 // [Return]:
2911 //
2912 //**************************************************************************
mhal_mhl_CbusConnectProc(MS_U8 ucCbusSelect)2913 void mhal_mhl_CbusConnectProc(MS_U8 ucCbusSelect)
2914 {
2915 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_MHL_RTERM);
2916
2917 #if(DMHL_LG_PRADA_PATCH)
2918 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, FALSE);
2919 #endif
2920
2921 mhal_mhl_CbusStucktoLow(TRUE);
2922 }
2923
2924 //**************************************************************************
2925 // [Function Name]:
2926 // mhal_mhl_CbusStucktoLowProc()
2927 // [Description]
2928 //
2929 // [Arguments]:
2930 //
2931 // [Return]:
2932 //
2933 //**************************************************************************
mhal_mhl_CbusStucktoLowProc(MS_U8 ucCbusSelect)2934 void mhal_mhl_CbusStucktoLowProc(MS_U8 ucCbusSelect)
2935 {
2936 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
2937
2938 #if(DMHL_LG_PRADA_PATCH)
2939 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
2940 #endif
2941
2942 mhal_mhl_CDRModeMonitor(ucCbusSelect, FALSE);
2943 }
2944
2945 //**************************************************************************
2946 // [Function Name]:
2947 // mhal_mhl_SourceChangeProc()
2948 // [Description]
2949 //
2950 // [Arguments]:
2951 //
2952 // [Return]:
2953 //
2954 //**************************************************************************
mhal_mhl_SourceChangeProc(MS_U8 ucCbusSelect)2955 void mhal_mhl_SourceChangeProc(MS_U8 ucCbusSelect)
2956 {
2957 if(mhal_mhl_CheckInputPort(ucCbusSelect))
2958 {
2959 //_mhal_mhl_ChangeScalerMainMux(TRUE);
2960 //_mhal_mhl_AudioPathSelect(TRUE);
2961 }
2962 else
2963 {
2964 //_mhal_mhl_ChangeScalerMainMux(FALSE);
2965 //_mhal_mhl_AudioPathSelect(FALSE);
2966 }
2967 }
2968
2969 //**************************************************************************
2970 // [Function Name]:
2971 // mhal_mhl_ClockModeSwitchProc()
2972 // [Description]
2973 //
2974 // [Arguments]:
2975 //
2976 // [Return]:
2977 //
2978 //**************************************************************************
mhal_mhl_ClockModeSwitchProc(MS_U8 ucCbusSelect,MS_BOOL bPPmode)2979 void mhal_mhl_ClockModeSwitchProc(MS_U8 ucCbusSelect, MS_BOOL bPPmode)
2980 {
2981 if(bPPmode)
2982 {
2983 _mhal_mhl_MhlPackedPixelModeSetting(ucCbusSelect);
2984 }
2985 else
2986 {
2987 _mhal_mhl_Mhl24bitsModeSetting(ucCbusSelect);
2988 }
2989 }
2990
2991 //**************************************************************************
2992 // [Function Name]:
2993 // mhal_mhl_CbusWakeupIntSetting()
2994 // [Description]
2995 //
2996 // [Arguments]:
2997 //
2998 // [Return]:
2999 //
3000 //**************************************************************************
mhal_mhl_CbusWakeupIntSetting(MS_U8 ucCbusSelect,MS_BOOL bFlag)3001 void mhal_mhl_CbusWakeupIntSetting(MS_U8 ucCbusSelect, MS_BOOL bFlag)
3002 {
3003 if(bFlag)
3004 {
3005 _mhal_mhl_CbusForceToStandby();
3006 mhal_mhl_CbusWakeupInterrupt(TRUE);
3007 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_CHARGE);
3008 }
3009 else
3010 {
3011 _mhal_mhl_MHLForceToAttach();
3012 mhal_mhl_CbusWakeupInterrupt(FALSE);
3013 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3014 }
3015 }
3016
3017 //**************************************************************************
3018 // [Function Name]:
3019 // mhal_mhl_RtermControlHWMode()
3020 // [Description]
3021 //
3022 // [Arguments]:
3023 //
3024 // [Return]:
3025 //
3026 //**************************************************************************
mhal_mhl_RtermControlHWMode(MS_U8 ucCbusSelect,MS_BOOL bFlag)3027 void mhal_mhl_RtermControlHWMode(MS_U8 ucCbusSelect, MS_BOOL bFlag)
3028 {
3029 MS_U16 ustemp = mhal_mhl_CbusStatus();
3030
3031 if(!bFlag) // HW to SW control rterm
3032 {
3033 if((ustemp & BMASK(1:0)) == 0x03)
3034 {
3035 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_MHL_RTERM);
3036 }
3037 else
3038 {
3039 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
3040 }
3041 }
3042
3043 _mhal_mhl_RtermHWControl(ucCbusSelect, bFlag);
3044 }
3045
3046 //**************************************************************************
3047 // [Function Name]:
3048 // mhal_mhl_AdjustSettingIControl()
3049 // [Description]
3050 //
3051 // [Arguments]:
3052 //
3053 // [Return]:
3054 //
3055 //**************************************************************************
mhal_mhl_AdjustSettingIControl(MS_U8 ucIControl)3056 void mhal_mhl_AdjustSettingIControl(MS_U8 ucIControl)
3057 {
3058 ucIControlValue = ucIControl;
3059 }
3060
3061 //**************************************************************************
3062 // [Function Name]:
3063 // mhal_mhl_AdjustImpedanceSetting()
3064 // [Description]
3065 //
3066 // [Arguments]:
3067 //
3068 // [Return]:
3069 //
3070 //**************************************************************************
mhal_mhl_AdjustImpedanceSetting(MS_U8 ucImpedance)3071 void mhal_mhl_AdjustImpedanceSetting(MS_U8 ucImpedance)
3072 {
3073 ucImpedanceValue = ucImpedance;
3074 }
3075
3076 //**************************************************************************
3077 // [Function Name]:
3078 // mhal_mhl_GetSignalStableFlag()
3079 // [Description]
3080 //
3081 // [Arguments]:
3082 //
3083 // [Return]:
3084 //
3085 //**************************************************************************
mhal_mhl_GetSignalStableFlag(void)3086 MS_BOOL mhal_mhl_GetSignalStableFlag(void)
3087 {
3088 return bMHLSignalStable;
3089 }
3090
3091 //**************************************************************************
3092 // [Function Name]:
3093 // mhal_mhl_PowerControl()
3094 // [Description]
3095 // MHL power control
3096 // [Arguments]:
3097 //
3098 // [Return]:
3099 //
3100 //**************************************************************************
mhal_mhl_LoadPowerOnTbl(void)3101 void mhal_mhl_LoadPowerOnTbl(void)
3102 {
3103 MS_U8 uctemp = 0;
3104
3105 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_ON_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3106 {
3107 W2BYTEMSK(tMHL_POWER_ON_TABLE[uctemp].addr, tMHL_POWER_ON_TABLE[uctemp].databuf, tMHL_POWER_ON_TABLE[uctemp].mask);
3108 }
3109
3110 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
3111 {
3112 _mhal_mhl_RxRtermControl(uctemp, RX_HDMI_RTERM);
3113 }
3114 }
3115
mhal_mhl_LoadPowerStandbyTbl(void)3116 void mhal_mhl_LoadPowerStandbyTbl(void)
3117 {
3118 MS_U8 uctemp = 0;
3119
3120 //_mhal_mhl_CbusForceToStandby();
3121
3122 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_SAVING_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3123 {
3124 W2BYTEMSK(tMHL_POWER_SAVING_TABLE[uctemp].addr, tMHL_POWER_SAVING_TABLE[uctemp].databuf, tMHL_POWER_SAVING_TABLE[uctemp].mask);
3125 }
3126
3127 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
3128 {
3129 _mhal_mhl_RxRtermControl(uctemp, RX_RTERM_OFF);
3130 mhal_mhl_VbusCharge(uctemp, VBUS_SW_CHARGE);
3131 }
3132 }
3133
mhal_mhl_LoadPowerDownTbl(void)3134 void mhal_mhl_LoadPowerDownTbl(void)
3135 {
3136 MS_U8 uctemp = 0;
3137
3138 //_mhal_mhl_CbusForceToStandby();
3139
3140 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_DOWN_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3141 {
3142 W2BYTEMSK(tMHL_POWER_DOWN_TABLE[uctemp].addr, tMHL_POWER_DOWN_TABLE[uctemp].databuf, tMHL_POWER_DOWN_TABLE[uctemp].mask);
3143 }
3144
3145 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
3146 {
3147 _mhal_mhl_RxRtermControl(uctemp, RX_RTERM_OFF);
3148 }
3149 }
3150
3151 //**************************************************************************
3152 // [Function Name]:
3153 // mhal_mhl_SetHPD()
3154 // [Description]
3155 // config HPD in combo(MHL/HDMI) port A
3156 // [Arguments]:
3157 //
3158 // [Return]:
3159 //
3160 //**************************************************************************
mhal_mhl_SetHPD(MS_BOOL bflag)3161 void mhal_mhl_SetHPD(MS_BOOL bflag)
3162 {
3163 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(0)); // [0]: reg_hplugc_mhl_en
3164
3165 if(bflag) // HPD is high
3166 {
3167 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen
3168 //msg_mhl(printf("**MHL_HPD is High"));
3169 }
3170 else // hpd is low
3171 {
3172 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen
3173 //msg_mhl(printf("**MHL_HPD is Low"));
3174 }
3175 }
3176
3177 //**************************************************************************
3178 // [Function Name]:
3179 // mhal_mhl_GetDDCErrorCode()
3180 // [Description]
3181 // Get DDC error code
3182 // [Arguments]:
3183 //
3184 // [Return]:
3185 //
3186 //**************************************************************************
mhal_mhl_GetDDCErrorCode(void)3187 MS_U8 mhal_mhl_GetDDCErrorCode(void)
3188 {
3189 return (R2BYTE(REG_MHL_CBUS_21)>>8);
3190 }
3191
3192 #if(MHL_CBUS_OPERATION_MODE == MHL_CBUS_HW_REPLY_MODE)
3193 //**************************************************************************
3194 // [Function Name]:
3195 // mhal_mhl_CheckSRAMReceiveBuffer()
3196 // [Description]
3197 //
3198 // [Arguments]:
3199 //
3200 // [Return]:
3201 //
3202 //**************************************************************************
mhal_mhl_CheckSRAMReceiveBuffer(void)3203 MS_BOOL mhal_mhl_CheckSRAMReceiveBuffer(void)
3204 {
3205 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE);
3206 }
3207
3208 //**************************************************************************
3209 // [Function Name]:
3210 // mhal_mhl_GetSRAMReceiveData()
3211 // [Description]
3212 //
3213 // [Arguments]:
3214 //
3215 // [Return]:
3216 //
3217 //**************************************************************************
mhal_mhl_GetSRAMReceiveData(void)3218 MS_U16 mhal_mhl_GetSRAMReceiveData(void)
3219 {
3220 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15));
3221
3222 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14));
3223
3224 return R2BYTE(REG_MHL_CBUS_0F);
3225 }
3226
3227 #endif
3228
3229 #if(DMHL_TEST_SIGNAL_SUPPORT)
3230 //**************************************************************************
3231 // [Function Name]:
3232 // mhal_mhl_AdjustCommonModeResistor()
3233 // [Description]:
3234 //
3235 // [Arguments]:
3236 //
3237 // [Return]:
3238 //
3239 //**************************************************************************
mhal_mhl_TestSignal(MS_BOOL bflag)3240 void mhal_mhl_TestSignal(MS_BOOL bflag)
3241 {
3242 if(bflag)
3243 {
3244 W2BYTEMSK(0x001106, BIT(10), BIT(10));
3245 }
3246 else
3247 {
3248 W2BYTEMSK(0x001106, 0, BIT(10));
3249 }
3250 }
3251
3252 #endif
3253
3254 #endif // _MHAL_MHL_C_
3255
3256