Lines Matching refs:BIT
151 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
152 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
154 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
163 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
166 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
168 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
171 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
175 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
180 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
181 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
182 {REG_PM_MHL_CBUS_30, BIT(1), BIT(1)}, // [1]: cbus conflict_int mask
183 …{REG_PM_MHL_CBUS_38, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused …
184 {REG_MHL_CBUS_14, BIT(13), BIT(13)}, // [13]: int mask for monitor_sram_full
185 {REG_MHL_CBUS_18, BIT(13), BIT(13)}, // [13]: send rcv_pkt_ddc_sw_overwrite_err_in mask
186 …{REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1…
187 {REG_MHL_CBUS_1B, BIT(1), BIT(1)}, // [1]: receive ddc packet valid mask
188 …{REG_MHL_CBUS_1F, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: ddc access edid timeout int mask, [1]: cl…
189 {REG_MHL_CBUS_21, BIT(5), BIT(5)}, // [5]: ddc error interrupt mask
190 …{REG_MHL_CBUS_22, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: ddc access hdcp timeout int…
191 {REG_MHL_CBUS_23, BIT(13), BIT(13)}, // [13]: send rcv_pkt_msc_sw_overwrite_err_in mask
192 {REG_MHL_CBUS_24, BIT(1), BIT(1)}, // [1]: send error interrupt mask
193 …{REG_MHL_CBUS_25, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: response_pkt_msc_hw_int mas…
194 {REG_MHL_CBUS_63, BIT(9), BIT(9)}, // [9]: dytycycle_bad_int mask
195 …{REG_MHL_CBUS_65, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: rcv_parity_err_int mask, [5…
196 …{REG_MHL_CBUS_78, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mas…
213 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
221 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
409 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
411 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
416 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
420 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
432 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
434 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
435 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
436 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
439 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
443 W2BYTEMSK(REG_COMBO_PHY0_P1_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
455 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
457 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
458 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
459 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
462 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
466 W2BYTEMSK(REG_COMBO_PHY0_P2_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
478 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
480 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
481 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
482 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
485 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
489 W2BYTEMSK(REG_COMBO_PHY0_P3_59_L, 0, BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
523 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
525 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
526 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
527 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
530 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
535 W2BYTEMSK(REG_COMBO_PHY0_P0_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
547 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
549 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
550 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
551 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
554 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
559 W2BYTEMSK(REG_COMBO_PHY0_P1_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
571 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
573 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
574 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
575 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
578 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
583 W2BYTEMSK(REG_COMBO_PHY0_P2_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
595 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
597 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
598 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
599 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
602 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
607 W2BYTEMSK(REG_COMBO_PHY0_P3_59_L, BIT(8), BIT(8)); in _mhal_mhl_Mhl24bitsModeSetting()
641 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
642 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
652 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
653 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
663 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
664 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
674 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
675 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
708 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
712 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
713 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
718 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
732 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
736 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
737 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
742 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(4), BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
756 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
761 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
766 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
784 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
785 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
790 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(12), BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
815 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
816 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode in _mhal_mhl_CbusForceToStandby()
831 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14)); in _mhal_mhl_MHLForceToAttach()
853 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
863 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
873 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
883 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
1008 if((R2BYTE(REG_COMBO_PHY0_P0_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1028 if((R2BYTE(REG_COMBO_PHY0_P1_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1048 if((R2BYTE(REG_COMBO_PHY0_P2_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1068 if((R2BYTE(REG_COMBO_PHY0_P3_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1108 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1118 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1128 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1138 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
1211 W2BYTEMSK(REG_PM_MHL_CBUS_21, 0, BIT(11)); in _mhal_mhl_CbusAndClockSelect()
1242 W2BYTEMSK(REG_PM_MHL_CBUS_20, bEnable? BIT(7): 0, BIT(7)); in _mhal_mhl_ForcePullDown100K()
1259 MS_U8 ucCommand = BIT(7) |BIT(6) |((ucOpCode &BMASK(2:0)) << 2); in _mhal_mhl_GetEMSCOneByteCRC()
1261 … ucAValue = GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BIT(3)) +2; in _mhal_mhl_GetEMSCOneByteCRC()
1262 … ucBValue = GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(4)) +GET_BIT(ucCommand &BIT(2)) +2; in _mhal_mhl_GetEMSCOneByteCRC()
1264 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCOneByteCRC()
1266 ucCommand |= BIT(1); in _mhal_mhl_GetEMSCOneByteCRC()
1269 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCOneByteCRC()
1271 ucCommand |= BIT(0); in _mhal_mhl_GetEMSCOneByteCRC()
1292 …MS_U16 ucCommand = BIT(13) |(((MS_U16)ucOpCode &BMASK(1:0)) << 11) |(((MS_U16)ucValue &BMASK(7:0))… in _mhal_mhl_GetEMSCTwoByteCRC()
1294 …T_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1295 …ucAValue = ucAValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BI… in _mhal_mhl_GetEMSCTwoByteCRC()
1296 …T_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1297 …ucBValue = ucBValue +GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BI… in _mhal_mhl_GetEMSCTwoByteCRC()
1298 …T_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1299 ucCValue = ucCValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +2; in _mhal_mhl_GetEMSCTwoByteCRC()
1301 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1303 ucCommand |= BIT(2); in _mhal_mhl_GetEMSCTwoByteCRC()
1306 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1308 ucCommand |= BIT(1); in _mhal_mhl_GetEMSCTwoByteCRC()
1311 if(ucCValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1313 ucCommand |= BIT(0); in _mhal_mhl_GetEMSCTwoByteCRC()
1333 …U8 ucCValue = GET_BIT(ucOpCode &BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(usCRCValus &BIT(6)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1334 …U8 ucDValue = GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(usCRCValus &BIT(5)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1335 …U8 ucEValue = GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(usCRCValus &BIT(4)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1336 …U8 ucFValue = GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(usCRCValus &BIT(3)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1337 …U8 ucGValue = GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(usCRCValus &BIT(2)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1338 …U8 ucHValue = GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(usCRCValus &BIT(1)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1339 …GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCVa… in _mhal_mhl_GetEMSCPayloadCRC()
1340 …MS_U8 ucJValue = GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1… in _mhal_mhl_GetEMSCPayloadCRC()
1341 MS_U8 ucKValue = GET_BIT(usCRCValus &BIT(13)); in _mhal_mhl_GetEMSCPayloadCRC()
1342 MS_U8 ucLValue = GET_BIT(usCRCValus &BIT(12)); in _mhal_mhl_GetEMSCPayloadCRC()
1343 MS_U8 ucMValue = GET_BIT(usCRCValus &BIT(11)); in _mhal_mhl_GetEMSCPayloadCRC()
1344 MS_U8 ucNValue = GET_BIT(usCRCValus &BIT(10)); in _mhal_mhl_GetEMSCPayloadCRC()
1345 MS_U8 ucOValue = GET_BIT(usCRCValus &BIT(9)); in _mhal_mhl_GetEMSCPayloadCRC()
1349 …BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(… in _mhal_mhl_GetEMSCPayloadCRC()
1350 …BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GE… in _mhal_mhl_GetEMSCPayloadCRC()
1351 …BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(… in _mhal_mhl_GetEMSCPayloadCRC()
1352 …BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GE… in _mhal_mhl_GetEMSCPayloadCRC()
1353 ucPValue = ucAValue +GET_BIT(usCRCValus &BIT(8)); in _mhal_mhl_GetEMSCPayloadCRC()
1355 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1357 usCommand |= BIT(15); in _mhal_mhl_GetEMSCPayloadCRC()
1360 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1362 usCommand |= BIT(14); in _mhal_mhl_GetEMSCPayloadCRC()
1365 if(ucCValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1367 usCommand |= BIT(13); in _mhal_mhl_GetEMSCPayloadCRC()
1370 if(ucDValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1372 usCommand |= BIT(12); in _mhal_mhl_GetEMSCPayloadCRC()
1375 if(ucEValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1377 usCommand |= BIT(11); in _mhal_mhl_GetEMSCPayloadCRC()
1380 if(ucFValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1382 usCommand |= BIT(10); in _mhal_mhl_GetEMSCPayloadCRC()
1385 if(ucGValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1387 usCommand |= BIT(9); in _mhal_mhl_GetEMSCPayloadCRC()
1390 if(ucHValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1392 usCommand |= BIT(8); in _mhal_mhl_GetEMSCPayloadCRC()
1395 if(ucIValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1397 usCommand |= BIT(7); in _mhal_mhl_GetEMSCPayloadCRC()
1400 if(ucJValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1402 usCommand |= BIT(6); in _mhal_mhl_GetEMSCPayloadCRC()
1405 if(ucKValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1407 usCommand |= BIT(5); in _mhal_mhl_GetEMSCPayloadCRC()
1410 if(ucLValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1412 usCommand |= BIT(4); in _mhal_mhl_GetEMSCPayloadCRC()
1415 if(ucMValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1417 usCommand |= BIT(3); in _mhal_mhl_GetEMSCPayloadCRC()
1420 if(ucNValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1422 usCommand |= BIT(2); in _mhal_mhl_GetEMSCPayloadCRC()
1425 if(ucOValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1427 usCommand |= BIT(1); in _mhal_mhl_GetEMSCPayloadCRC()
1430 if(ucPValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1432 usCommand |= BIT(0); in _mhal_mhl_GetEMSCPayloadCRC()
1461 W2BYTEMSK(REG_MHL_ECBUS_PHY_78, BIT(0), BIT(0)); in _mhal_mhl_ECbusInitialSetting()
1464 W2BYTEMSK(REG_MHL_ECBUS_2D, BIT(3), BIT(3)); in _mhal_mhl_ECbusInitialSetting()
1467 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
1471 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7] in _mhal_mhl_ECbusInitialSetting()
1472 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5)); in _mhal_mhl_ECbusInitialSetting()
1482 W2BYTEMSK(REG_MHL_ECBUS_PHY_13, BIT(4), BIT(4)); // in _mhal_mhl_ECbusInitialSetting()
1483 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, BIT(11), BIT(11)); // in _mhal_mhl_ECbusInitialSetting()
1503 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time in _mhal_mhl_ECbusInitialSetting()
1508 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x33, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1511 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1514 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(8), BIT(8)); in _mhal_mhl_ECbusInitialSetting()
1535 W2BYTEMSK(REG_MHL_ECBUS_36, 0, BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1539 W2BYTEMSK(REG_MHL_ECBUS_36, BIT(0), BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1542 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1557 W2BYTEMSK(REG_MHL_ECBUS_36, bEnableFlag? 0: BIT(12), BIT(12)); // eMSC receive int mask in _mhal_mhl_SetEMSCReceiveInterrupt()
1558 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, bEnableFlag? 0: BIT(0), BIT(0)); // ECbus PLL pd in _mhal_mhl_ECbusEnableSetting()
1590 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
1591 W2BYTEMSK(REG_MHL_ECBUS_PHY_6F, bEnableFlag? BIT(8): 0, BIT(8)); // ECbus clock detect in _mhal_mhl_ECbusEnableSetting()
1592 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1593 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1597 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(13), BIT(13)); // [13]: ECbus on in _mhal_mhl_ECbusEnableSetting()
1601 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off in _mhal_mhl_ECbusEnableSetting()
1617 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
1632 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(0), BIT(0)); in _mhal_mhl_CbusEngineReset()
1633 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(0)); in _mhal_mhl_CbusEngineReset()
1689 W2BYTEMSK(REG_COMBO_PHY0_P0_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1701 W2BYTEMSK(REG_COMBO_PHY0_P1_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1713 W2BYTEMSK(REG_COMBO_PHY0_P2_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1725 W2BYTEMSK(REG_COMBO_PHY0_P3_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1759 if(R2BYTE(REG_MHL_ECBUS_PHY_4D) & BIT(15)) in _mhal_mhl_ECbusStateChangeProc()
1764 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4] in _mhal_mhl_ECbusStateChangeProc()
1780 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));// in _mhal_mhl_ECbusStateChangeProc()
1784 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13)| BIT(12), BMASK(14:12)); // delay in _mhal_mhl_ECbusStateChangeProc()
1808 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1809 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1813 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeUpProc()
1831 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeDownProc()
1846 …W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_c… in _mhal_mhl_MHL3MuxSetting0()
1861 W2BYTEMSK(REG_MHL_ECBUS_23, BIT(15), BIT(15)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1863 while((R2BYTE(REG_MHL_ECBUS_23) & BIT(14)) == BIT(14)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1882 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1884 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
1911 if(usECbusData[ustemp] &BIT(15)) // Send case in _mhal_mhl_ParsingECbusCommand()
1915 if(usECbusData[usCounnter] &BIT(15)) in _mhal_mhl_ParsingECbusCommand()
1957 if((usECbusData[usCounnter] &BIT(15)) == 0) in _mhal_mhl_ParsingECbusCommand()
2042 usECbusCData[ustemp] = ucSendData |BIT(15); in _mhal_mhl_GetECbusCommand()
2340 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2360 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2370 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2474 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
2479 if((R2BYTE(REG_DVI_DTOP_DUAL_P0_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2489 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2491 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2515 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
2542 if((R2BYTE(REG_DVI_DTOP_DUAL_P1_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2552 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2554 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2603 if((R2BYTE(REG_DVI_DTOP_DUAL_P2_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2613 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2615 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2664 if((R2BYTE(REG_DVI_DTOP_DUAL_P3_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2674 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2676 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2746 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2750 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2773 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2777 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2790 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2794 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
2831 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2862 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2883 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
2914 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5)); in mhal_mhl_CbusFloating()
2918 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5)); in mhal_mhl_CbusFloating()
2936 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2940 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
2943 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag in mhal_mhl_CbusStucktoLow()
2960 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2964 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
2967 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag in mhal_mhl_CbusWakeupInterrupt()
3004 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3010 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3011 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3012 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
3015 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3041 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3042 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3043 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
3122 W2BYTEMSK(0x2B28, 0, BIT(11)); in mhal_mhl_initial()
3135 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3172 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3192 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3202 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3238 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3239 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3243 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3254 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3278 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3279 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3283 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3294 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3308 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3309 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3313 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3324 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3468 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3472 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
3490 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusStucktoLowFlag()
3494 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); in mhal_mhl_CbusStucktoLowFlag()
3512 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(7)) ?TRUE: FALSE); in mhal_mhl_CbusWakeupIntFlag()
3516 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); in mhal_mhl_CbusWakeupIntFlag()
3534 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(0)) ?TRUE: FALSE); in mhal_mhl_GetECbusStateChangeFlag()
3538 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
3558 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(12)) ?TRUE: FALSE); in mhal_mhl_GetEMSCReceiveFlag()
3562 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
3582 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(10)) // eMSC send pass interrupt. in mhal_mhl_GetEMSCSendStatus()
3584 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
3588 else if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(9)) // eMSC send fail interrupt. in mhal_mhl_GetEMSCSendStatus()
3590 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
3625 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send in mhal_mhl_CBusWrite()
3630 if((pdatabuf->databuf[uctemp]) &BIT(8)) in mhal_mhl_CBusWrite()
3660 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12)); in mhal_mhl_Cbus_SetPathEn()
3664 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13)); in mhal_mhl_Cbus_SetPathEn()
3694 if(!(reg_val &BIT(8))) // Received data in mhal_mhl_CbusIntCB()
3706 if(reg_val & BIT(15)) in mhal_mhl_CbusIntCB()
3712 *bIsCmdInData = (reg_val & BIT(8)) ? TRUE : FALSE; in mhal_mhl_CbusIntCB()
3728 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
4082 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4120 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4135 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4137 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
4159 W2BYTEMSK(0x001106, BIT(10), BIT(10)); in mhal_mhl_TestSignal()
4163 W2BYTEMSK(0x001106, 0, BIT(10)); in mhal_mhl_TestSignal()
4291 if(R2BYTE(REG_MHL_ECBUS_PHY_6F) &BIT(13)) // [13]: ECbus clock lock flag in mhal_mhl_GetECbusStatusFlag()
4300 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13)); in mhal_mhl_GetECbusStatusFlag()
4304 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(7)) // REG_MHL_CBUS2_3A[7] in mhal_mhl_GetECbusStatusFlag()
4309 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(15)) // REG_MHL_CBUS2_3A[15] in mhal_mhl_GetECbusStatusFlag()
4454 W2BYTEMSK(REG_MHL_ECBUS_1C, BIT(15), BIT(15)); in mhal_mhl_GetEMSCReceiveData()
4478 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
4489 W2BYTEMSK(REG_MHL_ECBUS_19, BIT(15), BIT(15)); // eMSC payload CRC ove in mhal_mhl_InsertEMSCSendData()
4494 W2BYTEMSK(REG_MHL_ECBUS_1B, BIT(15), BIT(15)); // REG_MHL_ECBUS2_1B[15] in mhal_mhl_InsertEMSCSendData()