Lines Matching refs:BIT
162 …{REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitra…
163 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
174 …{REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_dev…
177 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
182 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
186 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
191 …{REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_…
192 …{REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confir…
193 {REG_PM_MHL_CBUS_30, BIT(1), BIT(1)}, // [1]: cbus conflict_int mask
194 …{REG_PM_MHL_CBUS_38, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused …
195 {REG_MHL_CBUS_14, BIT(13), BIT(13)}, // [13]: int mask for monitor_sram_full
196 {REG_MHL_CBUS_18, BIT(13), BIT(13)}, // [13]: send rcv_pkt_ddc_sw_overwrite_err_in mask
197 …{REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1…
198 {REG_MHL_CBUS_1B, BIT(1), BIT(1)}, // [1]: receive ddc packet valid mask
199 …{REG_MHL_CBUS_1F, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: ddc access edid timeout int mask, [1]: cl…
200 {REG_MHL_CBUS_21, BIT(5), BIT(5)}, // [5]: ddc error interrupt mask
201 …{REG_MHL_CBUS_22, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: ddc access hdcp timeout int…
202 {REG_MHL_CBUS_23, BIT(13), BIT(13)}, // [13]: send rcv_pkt_msc_sw_overwrite_err_in mask
203 {REG_MHL_CBUS_24, BIT(1), BIT(1)}, // [1]: send error interrupt mask
204 …{REG_MHL_CBUS_25, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: response_pkt_msc_hw_int mas…
205 {REG_MHL_CBUS_63, BIT(9), BIT(9)}, // [9]: dytycycle_bad_int mask
206 …{REG_MHL_CBUS_65, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: rcv_parity_err_int mask, [5…
207 …{REG_MHL_CBUS_78, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mas…
224 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
232 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
410 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
413 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
414 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
417 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
434 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
436 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
437 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
438 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
441 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
458 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
460 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
461 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
462 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
465 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
482 … W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode in _mhal_mhl_HdmiBypassModeSetting()
484 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0)); in _mhal_mhl_HdmiBypassModeSetting()
485 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_HdmiBypassModeSetting()
486 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, 0, BIT(10)); // I-control PD overwrite write in _mhal_mhl_HdmiBypassModeSetting()
489 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
530 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
532 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
533 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
534 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
537 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
550 if(pMHLSignalStatus->ucImpedanceOffset &BIT(7)) in _mhal_mhl_Mhl24bitsModeSetting()
567 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
569 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
570 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
571 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
574 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
587 if(pMHLSignalStatus->ucImpedanceOffset &BIT(7)) in _mhal_mhl_Mhl24bitsModeSetting()
604 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
606 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
607 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
608 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
611 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
624 if(pMHLSignalStatus->ucImpedanceOffset &BIT(7)) in _mhal_mhl_Mhl24bitsModeSetting()
641 …W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel m… in _mhal_mhl_Mhl24bitsModeSetting()
643 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0)); in _mhal_mhl_Mhl24bitsModeSetting()
644 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_Mhl24bitsModeSetting()
645 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write in _mhal_mhl_Mhl24bitsModeSetting()
648 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, BIT(12) |0x30, BMASK(12:0)); in _mhal_mhl_Mhl24bitsModeSetting()
661 if(pMHLSignalStatus->ucImpedanceOffset &BIT(7)) in _mhal_mhl_Mhl24bitsModeSetting()
700 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
701 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
708 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
709 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
716 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
717 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
724 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode in _mhal_mhl_MhlPackedPixelModeSetting()
725 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble in _mhal_mhl_MhlPackedPixelModeSetting()
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term in _mhal_mhl_RxRtermControl()
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term in _mhal_mhl_RxRtermControl()
776 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term in _mhal_mhl_RxRtermControl()
781 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
786 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(4), BIT(4));// clock R-term in _mhal_mhl_RxRtermControl()
797 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
801 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term in _mhal_mhl_RxRtermControl()
802 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
807 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
818 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
822 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term in _mhal_mhl_RxRtermControl()
823 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
828 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(12), BIT(12));// clock R-term in _mhal_mhl_RxRtermControl()
852 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in _mhal_mhl_CbusForceToStandby()
853 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode in _mhal_mhl_CbusForceToStandby()
868 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14)); in _mhal_mhl_MHLForceToAttach()
888 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
894 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
900 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
906 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable in _mhal_mhl_AdjustCommonModeResistor()
939 if((R2BYTE(REG_COMBO_PHY0_P0_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
956 if((R2BYTE(REG_COMBO_PHY0_P1_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
973 if((R2BYTE(REG_COMBO_PHY0_P2_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
990 if((R2BYTE(REG_COMBO_PHY0_P3_41_L) &BIT(9)) == BIT(9)) in _mhal_mhl_CheckClockStatus()
1027 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8)); in _mhal_mhl_RtermHWControl()
1033 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9)); in _mhal_mhl_RtermHWControl()
1039 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10)); in _mhal_mhl_RtermHWControl()
1045 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11)); in _mhal_mhl_RtermHWControl()
1188 W2BYTEMSK(REG_PM_MHL_CBUS_20, bEnable? BIT(7): 0, BIT(7)); in _mhal_mhl_ForcePullDown100K()
1205 MS_U8 ucCommand = BIT(7) |BIT(6) |((ucOpCode &BMASK(2:0)) << 2); in _mhal_mhl_GetEMSCOneByteCRC()
1207 … ucAValue = GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BIT(3)) +2; in _mhal_mhl_GetEMSCOneByteCRC()
1208 … ucBValue = GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(4)) +GET_BIT(ucCommand &BIT(2)) +2; in _mhal_mhl_GetEMSCOneByteCRC()
1210 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCOneByteCRC()
1212 ucCommand |= BIT(1); in _mhal_mhl_GetEMSCOneByteCRC()
1215 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCOneByteCRC()
1217 ucCommand |= BIT(0); in _mhal_mhl_GetEMSCOneByteCRC()
1238 …MS_U16 ucCommand = BIT(13) |(((MS_U16)ucOpCode &BMASK(1:0)) << 11) |(((MS_U16)ucValue &BMASK(7:0))… in _mhal_mhl_GetEMSCTwoByteCRC()
1240 …T_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1241 …ucAValue = ucAValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BI… in _mhal_mhl_GetEMSCTwoByteCRC()
1242 …T_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1243 …ucBValue = ucBValue +GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BI… in _mhal_mhl_GetEMSCTwoByteCRC()
1244 …T_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCom… in _mhal_mhl_GetEMSCTwoByteCRC()
1245 ucCValue = ucCValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +2; in _mhal_mhl_GetEMSCTwoByteCRC()
1247 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1249 ucCommand |= BIT(2); in _mhal_mhl_GetEMSCTwoByteCRC()
1252 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1254 ucCommand |= BIT(1); in _mhal_mhl_GetEMSCTwoByteCRC()
1257 if(ucCValue &BIT(0)) in _mhal_mhl_GetEMSCTwoByteCRC()
1259 ucCommand |= BIT(0); in _mhal_mhl_GetEMSCTwoByteCRC()
1279 …U8 ucCValue = GET_BIT(ucOpCode &BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(usCRCValus &BIT(6)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1280 …U8 ucDValue = GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(usCRCValus &BIT(5)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1281 …U8 ucEValue = GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(usCRCValus &BIT(4)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1282 …U8 ucFValue = GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(usCRCValus &BIT(3)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1283 …U8 ucGValue = GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(usCRCValus &BIT(2)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1284 …U8 ucHValue = GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(usCRCValus &BIT(1)) +G… in _mhal_mhl_GetEMSCPayloadCRC()
1285 …GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCVa… in _mhal_mhl_GetEMSCPayloadCRC()
1286 …MS_U8 ucJValue = GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1… in _mhal_mhl_GetEMSCPayloadCRC()
1287 MS_U8 ucKValue = GET_BIT(usCRCValus &BIT(13)); in _mhal_mhl_GetEMSCPayloadCRC()
1288 MS_U8 ucLValue = GET_BIT(usCRCValus &BIT(12)); in _mhal_mhl_GetEMSCPayloadCRC()
1289 MS_U8 ucMValue = GET_BIT(usCRCValus &BIT(11)); in _mhal_mhl_GetEMSCPayloadCRC()
1290 MS_U8 ucNValue = GET_BIT(usCRCValus &BIT(10)); in _mhal_mhl_GetEMSCPayloadCRC()
1291 MS_U8 ucOValue = GET_BIT(usCRCValus &BIT(9)); in _mhal_mhl_GetEMSCPayloadCRC()
1295 …BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(… in _mhal_mhl_GetEMSCPayloadCRC()
1296 …BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GE… in _mhal_mhl_GetEMSCPayloadCRC()
1297 …BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(… in _mhal_mhl_GetEMSCPayloadCRC()
1298 …BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GE… in _mhal_mhl_GetEMSCPayloadCRC()
1299 ucPValue = ucAValue +GET_BIT(usCRCValus &BIT(8)); in _mhal_mhl_GetEMSCPayloadCRC()
1301 if(ucAValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1303 usCommand |= BIT(15); in _mhal_mhl_GetEMSCPayloadCRC()
1306 if(ucBValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1308 usCommand |= BIT(14); in _mhal_mhl_GetEMSCPayloadCRC()
1311 if(ucCValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1313 usCommand |= BIT(13); in _mhal_mhl_GetEMSCPayloadCRC()
1316 if(ucDValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1318 usCommand |= BIT(12); in _mhal_mhl_GetEMSCPayloadCRC()
1321 if(ucEValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1323 usCommand |= BIT(11); in _mhal_mhl_GetEMSCPayloadCRC()
1326 if(ucFValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1328 usCommand |= BIT(10); in _mhal_mhl_GetEMSCPayloadCRC()
1331 if(ucGValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1333 usCommand |= BIT(9); in _mhal_mhl_GetEMSCPayloadCRC()
1336 if(ucHValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1338 usCommand |= BIT(8); in _mhal_mhl_GetEMSCPayloadCRC()
1341 if(ucIValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1343 usCommand |= BIT(7); in _mhal_mhl_GetEMSCPayloadCRC()
1346 if(ucJValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1348 usCommand |= BIT(6); in _mhal_mhl_GetEMSCPayloadCRC()
1351 if(ucKValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1353 usCommand |= BIT(5); in _mhal_mhl_GetEMSCPayloadCRC()
1356 if(ucLValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1358 usCommand |= BIT(4); in _mhal_mhl_GetEMSCPayloadCRC()
1361 if(ucMValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1363 usCommand |= BIT(3); in _mhal_mhl_GetEMSCPayloadCRC()
1366 if(ucNValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1368 usCommand |= BIT(2); in _mhal_mhl_GetEMSCPayloadCRC()
1371 if(ucOValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1373 usCommand |= BIT(1); in _mhal_mhl_GetEMSCPayloadCRC()
1376 if(ucPValue &BIT(0)) in _mhal_mhl_GetEMSCPayloadCRC()
1378 usCommand |= BIT(0); in _mhal_mhl_GetEMSCPayloadCRC()
1407 W2BYTEMSK(REG_MHL_ECBUS_PHY_78, BIT(0), BIT(0)); in _mhal_mhl_ECbusInitialSetting()
1410 W2BYTEMSK(REG_MHL_ECBUS_2D, BIT(3), BIT(3)); in _mhal_mhl_ECbusInitialSetting()
1413 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en in _mhal_mhl_ECbusInitialSetting()
1417 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7] in _mhal_mhl_ECbusInitialSetting()
1418 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5)); in _mhal_mhl_ECbusInitialSetting()
1427 …W2BYTEMSK(REG_MHL_ECBUS_79, BIT(11)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 1) << 3)| (_mhal_mhl_GetEMSCT… in _mhal_mhl_ECbusInitialSetting()
1428 W2BYTEMSK(REG_MHL_ECBUS_PHY_13, BIT(4), BIT(4)); // in _mhal_mhl_ECbusInitialSetting()
1429 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, BIT(11), BIT(11)); // in _mhal_mhl_ECbusInitialSetting()
1449 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time in _mhal_mhl_ECbusInitialSetting()
1454 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x22, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4)); in _mhal_mhl_ECbusInitialSetting()
1460 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(8), BIT(8)); in _mhal_mhl_ECbusInitialSetting()
1481 W2BYTEMSK(REG_MHL_ECBUS_36, 0, BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1485 W2BYTEMSK(REG_MHL_ECBUS_36, BIT(0), BIT(0)); // Ecbus state change int mask in _mhal_mhl_SetECbusStateChangeInterrupt()
1488 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear in _mhal_mhl_SetECbusStateChangeInterrupt()
1503 W2BYTEMSK(REG_MHL_ECBUS_36, bEnableFlag? 0: BIT(12), BIT(12)); // eMSC receive int mask in _mhal_mhl_SetEMSCReceiveInterrupt()
1504 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear in _mhal_mhl_SetEMSCReceiveInterrupt()
1534 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, bEnableFlag? 0: BIT(0), BIT(0)); // ECbus PLL pd in _mhal_mhl_ECbusEnableSetting()
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); // in _mhal_mhl_ECbusEnableSetting()
1537 W2BYTEMSK(REG_MHL_ECBUS_PHY_6F, bEnableFlag? BIT(8): 0, BIT(8)); // ECbus clock detect in _mhal_mhl_ECbusEnableSetting()
1538 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1539 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13)); in _mhal_mhl_ECbusEnableSetting()
1543 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(13), BIT(13)); // [13]: ECbus on in _mhal_mhl_ECbusEnableSetting()
1547 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off in _mhal_mhl_ECbusEnableSetting()
1568 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1569 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1571 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13)); in _mhal_mhl_ECbusBISTSetting()
1586 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, BIT(8), BIT(8)); in _mhal_mhl_ECbusBISTSetting()
1598 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off in _mhal_mhl_ECbusBISTSetting()
1601 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1602 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13), BIT(13)); in _mhal_mhl_ECbusBISTSetting()
1607 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0, BIT(8)); in _mhal_mhl_ECbusBISTSetting()
1623 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux in _mhal_mhl_ECbusDmuxEnable()
1638 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(0), BIT(0)); in _mhal_mhl_CbusEngineReset()
1639 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(0)); in _mhal_mhl_CbusEngineReset()
1686 W2BYTEMSK(REG_MHL_ECBUS_0F, bEnableFlag? (BIT(8)| 0x4): 0, BIT(8)| BMASK(3:0)); in _mhal_mhl_ECbusStateOverwrite()
1708 W2BYTEMSK(REG_COMBO_PHY0_P0_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1718 W2BYTEMSK(REG_COMBO_PHY0_P1_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1728 W2BYTEMSK(REG_COMBO_PHY0_P2_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1738 W2BYTEMSK(REG_COMBO_PHY0_P3_60_L, bEnableFlag? 0: BIT(5), BIT(5)); in _mhal_mhl_Version3PhyEnable()
1765 W2BYTEMSK(REG_MHL_ECBUS_3D, BIT(1), BIT(1)); in _mhal_mhl_SetECbusBISTTrigger()
1766 W2BYTEMSK(REG_MHL_ECBUS_2A, BIT(12), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1770 W2BYTEMSK(REG_MHL_ECBUS_2A, BIT(13), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1771 W2BYTEMSK(REG_MHL_ECBUS_3D, 0, BIT(1)); in _mhal_mhl_SetECbusBISTTrigger()
1777 W2BYTEMSK(REG_MHL_ECBUS_2E, bEnableFlag? BIT(12): BIT(13), BMASK(13:12)); in _mhal_mhl_SetECbusBISTTrigger()
1821 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1822 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status in _mhal_mhl_ECbusModeUpProc()
1826 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeUpProc()
1844 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13)); in _mhal_mhl_ECbusModeDownProc()
1859 …W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_c… in _mhal_mhl_MHL3MuxSetting0()
1874 W2BYTEMSK(REG_MHL_ECBUS_23, BIT(15), BIT(15)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1876 while((R2BYTE(REG_MHL_ECBUS_23) & BIT(14)) == BIT(14)); in _mhal_mhl_GetSRAMReceiveEMSCData()
1895 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1897 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
1924 if(usECbusData[ustemp] &BIT(15)) // Send case in _mhal_mhl_ParsingECbusCommand()
1928 if(usECbusData[usCounnter] &BIT(15)) in _mhal_mhl_ParsingECbusCommand()
1970 if((usECbusData[usCounnter] &BIT(15)) == 0) in _mhal_mhl_ParsingECbusCommand()
2084 …W2BYTEMSK(REG_MHL_ECBUS_7A, bEnableFlag? BIT(5)| BIT(4)| BMASK(3:0): 0, BIT(5)| BIT(4)| BMASK(3:0)… in _mhal_mhl_BISTECbusEnable()
2086 W2BYTEMSK(REG_MHL_ECBUS_2D, bEnableFlag? BIT(4): BIT(5), BMASK(5:4)); in _mhal_mhl_BISTECbusEnable()
2105 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0)); in _mhal_mhl_BISTAVLinkEnable()
2109 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, BIT(1), BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2110 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, 0, BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2118 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0)); in _mhal_mhl_BISTAVLinkEnable()
2122 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, BIT(1), BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2123 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, 0, BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2131 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0)); in _mhal_mhl_BISTAVLinkEnable()
2135 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, BIT(1), BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2136 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, 0, BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2144 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0)); in _mhal_mhl_BISTAVLinkEnable()
2148 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, BIT(1), BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2149 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, 0, BIT(1)); in _mhal_mhl_BISTAVLinkEnable()
2175 if(R2BYTE(REG_MHL_ECBUS_30) &BIT(15)) in _mhal_mhl_GetBISTECbusErrorCount()
2248 MS_BOOL bDEChangeFlag = ((R2BYTE(REG_HDMI_DUAL_0_02_L) & BIT(5)) ? TRUE : FALSE); in _mhal_mhl_CheckDEChangeFlag()
2253 W2BYTE(REG_HDMI_DUAL_0_02_L, BIT(5)); in _mhal_mhl_CheckDEChangeFlag()
2291 W2BYTEMSK(REG_COMBO_PHY1_P0_49_L, BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQSetting()
2292 W2BYTEMSK(REG_COMBO_PHY0_P0_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2293 W2BYTEMSK(REG_COMBO_PHY1_P0_11_L, BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQSetting()
2298 W2BYTEMSK(REG_COMBO_PHY0_P0_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2306 W2BYTEMSK(REG_COMBO_PHY1_P1_49_L, BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQSetting()
2307 W2BYTEMSK(REG_COMBO_PHY0_P1_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2308 W2BYTEMSK(REG_COMBO_PHY1_P1_11_L, BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQSetting()
2313 W2BYTEMSK(REG_COMBO_PHY0_P1_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2321 W2BYTEMSK(REG_COMBO_PHY1_P2_49_L, BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQSetting()
2322 W2BYTEMSK(REG_COMBO_PHY0_P2_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2323 W2BYTEMSK(REG_COMBO_PHY1_P2_11_L, BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQSetting()
2328 W2BYTEMSK(REG_COMBO_PHY0_P2_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2336 W2BYTEMSK(REG_COMBO_PHY1_P3_49_L, BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQSetting()
2337 W2BYTEMSK(REG_COMBO_PHY0_P3_29_L, BIT(8), BMASK(15:0)); in _mhal_mhl_MHL30AutoEQSetting()
2338 W2BYTEMSK(REG_COMBO_PHY1_P3_11_L, BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQSetting()
2343 W2BYTEMSK(REG_COMBO_PHY0_P3_26_L, BIT(11)| BIT(9), BMASK(13:8)); in _mhal_mhl_MHL30AutoEQSetting()
2372 W2BYTEMSK(REG_COMBO_PHY0_P0_33_L, BIT(2), BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2376 W2BYTEMSK(REG_COMBO_PHY0_P0_33_L, 0, BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2383 W2BYTEMSK(REG_COMBO_PHY0_P1_33_L, BIT(2), BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2387 W2BYTEMSK(REG_COMBO_PHY0_P1_33_L, 0, BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2394 W2BYTEMSK(REG_COMBO_PHY0_P2_33_L, BIT(2), BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2398 W2BYTEMSK(REG_COMBO_PHY0_P2_33_L, 0, BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2405 W2BYTEMSK(REG_COMBO_PHY0_P3_33_L, BIT(2), BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2409 W2BYTEMSK(REG_COMBO_PHY0_P3_33_L, 0, BIT(2)); in _mhal_mhl_MHL3AutoEQTrigger()
2440 if(R2BYTE(REG_COMBO_PHY0_P0_41_L) &BIT(8)) in _mhal_mhl_GetAutoEQDoneFlag()
2452 if(R2BYTE(REG_COMBO_PHY0_P1_41_L) &BIT(8)) in _mhal_mhl_GetAutoEQDoneFlag()
2464 if(R2BYTE(REG_COMBO_PHY0_P2_41_L) &BIT(8)) in _mhal_mhl_GetAutoEQDoneFlag()
2476 if(R2BYTE(REG_COMBO_PHY0_P3_41_L) &BIT(8)) in _mhal_mhl_GetAutoEQDoneFlag()
2513 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2519 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2524 W2BYTEMSK(REG_COMBO_PHY0_P0_15_L, bAutoEQEnable? BIT(15): 0, BIT(15)); in _mhal_mhl_MHL30AutoEQEnable()
2525 W2BYTEMSK(REG_COMBO_PHY1_P0_44_L, bAutoEQEnable? 0: BIT(0), BIT(0)); in _mhal_mhl_MHL30AutoEQEnable()
2526 W2BYTEMSK(REG_COMBO_PHY1_P0_49_L, bAutoEQEnable? 0: BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQEnable()
2527 W2BYTEMSK(REG_COMBO_PHY1_P0_11_L, bAutoEQEnable? 0: BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQEnable()
2537 W2BYTEMSK(REG_COMBO_PHY0_P1_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2543 W2BYTEMSK(REG_COMBO_PHY0_P1_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2548 W2BYTEMSK(REG_COMBO_PHY0_P1_15_L, bAutoEQEnable? BIT(15): 0, BIT(15)); in _mhal_mhl_MHL30AutoEQEnable()
2549 W2BYTEMSK(REG_COMBO_PHY1_P1_44_L, bAutoEQEnable? 0: BIT(0), BIT(0)); in _mhal_mhl_MHL30AutoEQEnable()
2550 W2BYTEMSK(REG_COMBO_PHY1_P1_49_L, bAutoEQEnable? 0: BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQEnable()
2551 W2BYTEMSK(REG_COMBO_PHY1_P1_11_L, bAutoEQEnable? 0: BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQEnable()
2561 W2BYTEMSK(REG_COMBO_PHY0_P2_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2567 W2BYTEMSK(REG_COMBO_PHY0_P2_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2572 W2BYTEMSK(REG_COMBO_PHY0_P2_15_L, bAutoEQEnable? BIT(15): 0, BIT(15)); in _mhal_mhl_MHL30AutoEQEnable()
2573 W2BYTEMSK(REG_COMBO_PHY1_P2_44_L, bAutoEQEnable? 0: BIT(0), BIT(0)); in _mhal_mhl_MHL30AutoEQEnable()
2574 W2BYTEMSK(REG_COMBO_PHY1_P2_49_L, bAutoEQEnable? 0: BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQEnable()
2575 W2BYTEMSK(REG_COMBO_PHY1_P2_11_L, bAutoEQEnable? 0: BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQEnable()
2585 W2BYTEMSK(REG_COMBO_PHY0_P3_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2591 W2BYTEMSK(REG_COMBO_PHY0_P3_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2596 W2BYTEMSK(REG_COMBO_PHY0_P3_15_L, bAutoEQEnable? BIT(15): 0, BIT(15)); in _mhal_mhl_MHL30AutoEQEnable()
2597 W2BYTEMSK(REG_COMBO_PHY1_P3_44_L, bAutoEQEnable? 0: BIT(0), BIT(0)); in _mhal_mhl_MHL30AutoEQEnable()
2598 W2BYTEMSK(REG_COMBO_PHY1_P3_49_L, bAutoEQEnable? 0: BIT(5), BIT(5)); in _mhal_mhl_MHL30AutoEQEnable()
2599 W2BYTEMSK(REG_COMBO_PHY1_P3_11_L, bAutoEQEnable? 0: BIT(4), BIT(4)); in _mhal_mhl_MHL30AutoEQEnable()
2827 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2833 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2839 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2845 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE); in mhal_mhl_CableDetect()
2927 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
2938 if((R2BYTE(REG_DVI_DTOP_DUAL_P0_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
2948 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
2950 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
2987 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
3010 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3021 if((R2BYTE(REG_DVI_DTOP_DUAL_P1_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
3031 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
3033 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
3070 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
3093 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3104 if((R2BYTE(REG_DVI_DTOP_DUAL_P2_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
3114 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
3116 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
3176 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3187 if((R2BYTE(REG_DVI_DTOP_DUAL_P3_31_L) &BIT(6)) == BIT(6)) // DE stable in mhal_mhl_CDRModeMonitor()
3197 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, BIT(13), BIT(13)); in mhal_mhl_CDRModeMonitor()
3199 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, 0, BIT(13)); in mhal_mhl_CDRModeMonitor()
3236 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
3274 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3278 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3288 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3292 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3302 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3306 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3316 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3320 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8)); in mhal_mhl_CbusIsolate()
3354 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3372 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3390 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3408 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0)); in mhal_mhl_VbusCharge()
3438 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5)); in mhal_mhl_CbusFloating()
3442 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5)); in mhal_mhl_CbusFloating()
3460 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
3464 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask in mhal_mhl_CbusStucktoLow()
3467 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag in mhal_mhl_CbusStucktoLow()
3484 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
3488 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask in mhal_mhl_CbusWakeupInterrupt()
3491 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag in mhal_mhl_CbusWakeupInterrupt()
3528 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable in mhal_mhl_LoadEDID()
3534 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger in mhal_mhl_LoadEDID()
3535 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_LoadEDID()
3536 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5)); in mhal_mhl_LoadEDID()
3539 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable in mhal_mhl_LoadEDID()
3565 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger in mhal_mhl_ReadEDID()
3566 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0)); in mhal_mhl_ReadEDID()
3567 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4)); in mhal_mhl_ReadEDID()
3644 W2BYTEMSK(0x2B28, 0, BIT(11)); in mhal_mhl_initial()
3657 …W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask in mhal_mhl_initial()
3692 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3698 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3704 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3710 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11)); in mhal_mhl_InvertCableDetect()
3742 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3743 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3747 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3758 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3769 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3770 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3774 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3785 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3796 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3797 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3801 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3812 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3823 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3824 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7)); in mhal_mhl_VbusConfigSetting()
3828 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0)); in mhal_mhl_VbusConfigSetting()
3839 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8)); in mhal_mhl_VbusConfigSetting()
3979 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusIsMscMsgReceived()
3983 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); in mhal_mhl_CbusIsMscMsgReceived()
4001 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(3)) ?TRUE: FALSE); in mhal_mhl_CbusStucktoLowFlag()
4005 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); in mhal_mhl_CbusStucktoLowFlag()
4023 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(7)) ?TRUE: FALSE); in mhal_mhl_CbusWakeupIntFlag()
4027 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); in mhal_mhl_CbusWakeupIntFlag()
4045 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(0)) ?TRUE: FALSE); in mhal_mhl_GetECbusStateChangeFlag()
4049 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); in mhal_mhl_GetECbusStateChangeFlag()
4072 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(12)) ?TRUE: FALSE); in mhal_mhl_GetEMSCReceiveFlag()
4076 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); in mhal_mhl_GetEMSCReceiveFlag()
4096 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(10)) // eMSC send pass interrupt. in mhal_mhl_GetEMSCSendStatus()
4098 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear in mhal_mhl_GetEMSCSendStatus()
4102 else if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(9)) // eMSC send fail interrupt. in mhal_mhl_GetEMSCSendStatus()
4104 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear in mhal_mhl_GetEMSCSendStatus()
4137 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send in mhal_mhl_CBusWrite()
4144 if((pdatabuf->databuf[uctemp]) &BIT(8)) in mhal_mhl_CBusWrite()
4175 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12)); in mhal_mhl_Cbus_SetPathEn()
4179 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13)); in mhal_mhl_Cbus_SetPathEn()
4209 if(!(reg_val &BIT(8))) // Received data in mhal_mhl_CbusIntCB()
4221 if(reg_val & BIT(15)) in mhal_mhl_CbusIntCB()
4227 *bIsCmdInData = (reg_val & BIT(8)) ? TRUE : FALSE; in mhal_mhl_CbusIntCB()
4243 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO in mhal_mhl_CbusIntCB()
4544 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen in mhal_mhl_SetHPD()
4580 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4595 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4597 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
4619 W2BYTEMSK(0x001106, BIT(10), BIT(10)); in mhal_mhl_TestSignal()
4623 W2BYTEMSK(0x001106, 0, BIT(10)); in mhal_mhl_TestSignal()
4734 if(R2BYTE(REG_MHL_ECBUS_PHY_6F) &BIT(13)) // [13]: ECbus clock lock flag in mhal_mhl_GetECbusStatusFlag()
4743 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13)); in mhal_mhl_GetECbusStatusFlag()
4747 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(7)) // REG_MHL_CBUS2_3A[7] in mhal_mhl_GetECbusStatusFlag()
4752 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(15)) // REG_MHL_CBUS2_3A[15] in mhal_mhl_GetECbusStatusFlag()
4892 usBISTAVLinkSettingValue = usBISTAVLinkSettingValue| BIT(15); in mhal_mhl_SetBISTParameterInfo()
4904 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_71_L, 0, BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4908 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_71_L, BIT(0), BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4921 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_71_L, 0, BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4925 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_71_L, BIT(0), BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4938 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_71_L, 0, BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4942 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_71_L, BIT(0), BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4955 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_73_L, 0, BIT(0)); in mhal_mhl_SetBISTParameterInfo()
4959 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_73_L, BIT(0), BIT(0)); in mhal_mhl_SetBISTParameterInfo()
5042 W2BYTEMSK(REG_MHL_ECBUS_1C, BIT(15), BIT(15)); in mhal_mhl_GetEMSCReceiveData()
5066 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
5077 W2BYTEMSK(REG_MHL_ECBUS_19, BIT(15), BIT(15)); // eMSC payload CRC ove in mhal_mhl_InsertEMSCSendData()
5082 W2BYTEMSK(REG_MHL_ECBUS_1B, BIT(15), BIT(15)); // REG_MHL_ECBUS2_1B[15] in mhal_mhl_InsertEMSCSendData()