Home
last modified time | relevance | path

Searched refs:rd_cfg (Results 1 – 25 of 46) sorted by relevance

12

/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu1_v2.c392 MppDevRegRdCfg rd_cfg; in hal_jpege_vepu1_start() local
405 rd_cfg.reg = ctx->regs; in hal_jpege_vepu1_start()
406 rd_cfg.size = reg_size; in hal_jpege_vepu1_start()
407 rd_cfg.offset = 0; in hal_jpege_vepu1_start()
409 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_jpege_vepu1_start()
527 MppDevRegRdCfg rd_cfg; in hal_jpege_vepu1_part_start() local
540 rd_cfg.reg = ctx->regs_out; in hal_jpege_vepu1_part_start()
541 rd_cfg.size = reg_size; in hal_jpege_vepu1_part_start()
542 rd_cfg.offset = 0; in hal_jpege_vepu1_part_start()
544 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_jpege_vepu1_part_start()
H A Dhal_jpege_vepu2_v2.c693 MppDevRegRdCfg rd_cfg; in multi_core_start() local
705 rd_cfg.reg = ctx_ext->regs_out[i]; in multi_core_start()
706 rd_cfg.size = reg_size; in multi_core_start()
707 rd_cfg.offset = 0; in multi_core_start()
709 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in multi_core_start()
815 MppDevRegRdCfg rd_cfg; in hal_jpege_vepu2_start() local
830 rd_cfg.reg = regs; in hal_jpege_vepu2_start()
831 rd_cfg.size = reg_size; in hal_jpege_vepu2_start()
832 rd_cfg.offset = 0; in hal_jpege_vepu2_start()
834 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_jpege_vepu2_start()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu2.c249 MppDevRegRdCfg rd_cfg; in hal_vpu2_h263d_start() local
261 rd_cfg.reg = regs; in hal_vpu2_h263d_start()
262 rd_cfg.size = sizeof(Vpu2H263dRegSet_t); in hal_vpu2_h263d_start()
263 rd_cfg.offset = 0; in hal_vpu2_h263d_start()
265 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vpu2_h263d_start()
H A Dhal_h263d_vdpu1.c248 MppDevRegRdCfg rd_cfg; in hal_vpu1_h263d_start() local
260 rd_cfg.reg = regs; in hal_vpu1_h263d_start()
261 rd_cfg.size = sizeof(Vpu1H263dRegSet_t); in hal_vpu1_h263d_start()
262 rd_cfg.offset = 0; in hal_vpu1_h263d_start()
264 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vpu1_h263d_start()
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_rkv.c824 MppDevRegRdCfg rd_cfg; in hal_avs2d_rkv_start() local
880 rd_cfg.reg = &regs->irq_status; in hal_avs2d_rkv_start()
881 rd_cfg.size = sizeof(regs->irq_status); in hal_avs2d_rkv_start()
882 rd_cfg.offset = OFFSET_INTERRUPT_REGS; in hal_avs2d_rkv_start()
883 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avs2d_rkv_start()
890 rd_cfg.reg = &regs->avs2d_param; in hal_avs2d_rkv_start()
891 rd_cfg.size = sizeof(regs->avs2d_param); in hal_avs2d_rkv_start()
892 rd_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_avs2d_rkv_start()
893 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avs2d_rkv_start()
900 rd_cfg.reg = &regs->statistic; in hal_avs2d_rkv_start()
[all …]
H A Dhal_avs2d_vdpu382.c890 MppDevRegRdCfg rd_cfg; in hal_avs2d_vdpu382_start() local
946 rd_cfg.reg = &regs->irq_status; in hal_avs2d_vdpu382_start()
947 rd_cfg.size = sizeof(regs->irq_status); in hal_avs2d_vdpu382_start()
948 rd_cfg.offset = OFFSET_INTERRUPT_REGS; in hal_avs2d_vdpu382_start()
949 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avs2d_vdpu382_start()
956 rd_cfg.reg = &regs->avs2d_param; in hal_avs2d_vdpu382_start()
957 rd_cfg.size = sizeof(regs->avs2d_param); in hal_avs2d_vdpu382_start()
958 rd_cfg.offset = OFFSET_CODEC_PARAMS_REGS; in hal_avs2d_vdpu382_start()
959 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avs2d_vdpu382_start()
966 rd_cfg.reg = &regs->statistic; in hal_avs2d_vdpu382_start()
[all …]
H A Dhal_avs2d_vdpu383.c734 MppDevRegRdCfg rd_cfg; in hal_avs2d_vdpu383_start() local
772 rd_cfg.reg = &regs->ctrl_regs.reg15; in hal_avs2d_vdpu383_start()
773 rd_cfg.size = sizeof(regs->ctrl_regs.reg15); in hal_avs2d_vdpu383_start()
774 rd_cfg.offset = OFFSET_INTERRUPT_REGS; in hal_avs2d_vdpu383_start()
775 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avs2d_vdpu383_start()
783 rd_cfg.reg = reg_ctx->reg_out; in hal_avs2d_vdpu383_start()
784 rd_cfg.size = sizeof(reg_ctx->reg_out); in hal_avs2d_vdpu383_start()
785 rd_cfg.offset = 0; in hal_avs2d_vdpu383_start()
786 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avs2d_vdpu383_start()
/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu1.c267 MppDevRegRdCfg rd_cfg; in hal_m2vd_vdpu1_start() local
281 rd_cfg.reg = regs; in hal_m2vd_vdpu1_start()
282 rd_cfg.size = reg_size; in hal_m2vd_vdpu1_start()
283 rd_cfg.offset = 0; in hal_m2vd_vdpu1_start()
285 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_m2vd_vdpu1_start()
H A Dhal_m2vd_vdpu2.c339 MppDevRegRdCfg rd_cfg; in hal_m2vd_vdpu2_start() local
353 rd_cfg.reg = regs; in hal_m2vd_vdpu2_start()
354 rd_cfg.size = reg_size; in hal_m2vd_vdpu2_start()
355 rd_cfg.offset = 0; in hal_m2vd_vdpu2_start()
357 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_m2vd_vdpu2_start()
/rockchip-linux_mpp/mpp/hal/vpu/mpg4d/
H A Dhal_m4vd_vdpu2.c415 MppDevRegRdCfg rd_cfg; in vdpu2_mpg4d_start() local
428 rd_cfg.reg = regs; in vdpu2_mpg4d_start()
429 rd_cfg.size = reg_size; in vdpu2_mpg4d_start()
430 rd_cfg.offset = 0; in vdpu2_mpg4d_start()
432 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in vdpu2_mpg4d_start()
H A Dhal_m4vd_vdpu1.c417 MppDevRegRdCfg rd_cfg; in vdpu1_mpg4d_start() local
430 rd_cfg.reg = regs; in vdpu1_mpg4d_start()
431 rd_cfg.size = reg_size; in vdpu1_mpg4d_start()
432 rd_cfg.offset = 0; in vdpu1_mpg4d_start()
434 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in vdpu1_mpg4d_start()
/rockchip-linux_mpp/mpp/hal/rkdec/vp9d/
H A Dhal_vp9d_rkv.c550 MppDevRegRdCfg rd_cfg; in hal_vp9d_rkv_start() local
563 rd_cfg.reg = hw_ctx->hw_regs; in hal_vp9d_rkv_start()
564 rd_cfg.size = reg_size; in hal_vp9d_rkv_start()
565 rd_cfg.offset = 0; in hal_vp9d_rkv_start()
567 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vp9d_rkv_start()
/rockchip-linux_mpp/mpp/hal/vpu/vp8d/
H A Dhal_vp8d_vdpu2.c652 MppDevRegRdCfg rd_cfg; in hal_vp8d_vdpu2_start() local
665 rd_cfg.reg = regs; in hal_vp8d_vdpu2_start()
666 rd_cfg.size = reg_size; in hal_vp8d_vdpu2_start()
667 rd_cfg.offset = 0; in hal_vp8d_vdpu2_start()
669 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vp8d_vdpu2_start()
H A Dhal_vp8d_vdpu1.c641 MppDevRegRdCfg rd_cfg; in hal_vp8d_vdpu1_start() local
654 rd_cfg.reg = regs; in hal_vp8d_vdpu1_start()
655 rd_cfg.size = reg_size; in hal_vp8d_vdpu1_start()
656 rd_cfg.offset = 0; in hal_vp8d_vdpu1_start()
658 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vp8d_vdpu1_start()
/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_vdpu1.c583 MppDevRegRdCfg rd_cfg; in hal_avsd_vdpu1_start() local
596 rd_cfg.reg = p_hal->p_regs; in hal_avsd_vdpu1_start()
597 rd_cfg.size = reg_size; in hal_avsd_vdpu1_start()
598 rd_cfg.offset = 0; in hal_avsd_vdpu1_start()
600 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avsd_vdpu1_start()
H A Dhal_avsd_vdpu2.c581 MppDevRegRdCfg rd_cfg; in hal_avsd_vdpu2_start() local
594 rd_cfg.reg = p_hal->p_regs; in hal_avsd_vdpu2_start()
595 rd_cfg.size = reg_size; in hal_avsd_vdpu2_start()
596 rd_cfg.offset = 0; in hal_avsd_vdpu2_start()
598 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avsd_vdpu2_start()
H A Dhal_avsd_plus.c691 MppDevRegRdCfg rd_cfg; in hal_avsd_plus_start() local
723 rd_cfg.reg = p_hal->p_regs; in hal_avsd_plus_start()
724 rd_cfg.size = AVSD_REGISTERS * sizeof(RK_U32); in hal_avsd_plus_start()
725 rd_cfg.offset = 0; in hal_avsd_plus_start()
727 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_avsd_plus_start()
/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_vepu1_v2.c387 MppDevRegRdCfg rd_cfg; in hal_vp8e_vepu1_start_v2() local
400 rd_cfg.reg = ctx->regs; in hal_vp8e_vepu1_start_v2()
401 rd_cfg.size = reg_size; in hal_vp8e_vepu1_start_v2()
402 rd_cfg.offset = 0; in hal_vp8e_vepu1_start_v2()
404 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vp8e_vepu1_start_v2()
H A Dhal_vp8e_vepu2_v2.c391 MppDevRegRdCfg rd_cfg; in hal_vp8e_vepu2_start_v2() local
404 rd_cfg.reg = ctx->regs; in hal_vp8e_vepu2_start_v2()
405 rd_cfg.size = reg_size; in hal_vp8e_vepu2_start_v2()
406 rd_cfg.offset = 0; in hal_vp8e_vepu2_start_v2()
408 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_vp8e_vepu2_start_v2()
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_rkv_reg.c717 MppDevRegRdCfg rd_cfg; in rkv_h264d_start() local
730 rd_cfg.reg = p_regs; in rkv_h264d_start()
731 rd_cfg.size = reg_size; in rkv_h264d_start()
732 rd_cfg.offset = 0; in rkv_h264d_start()
734 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg); in rkv_h264d_start()
H A Dhal_h264d_vdpu382.c1077 MppDevRegRdCfg rd_cfg; in vdpu382_h264d_start() local
1138 rd_cfg.reg = &regs->irq_status; in vdpu382_h264d_start()
1139 rd_cfg.size = sizeof(regs->irq_status); in vdpu382_h264d_start()
1140 rd_cfg.offset = OFFSET_INTERRUPT_REGS; in vdpu382_h264d_start()
1142 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in vdpu382_h264d_start()
1148 rd_cfg.reg = &regs->statistic; in vdpu382_h264d_start()
1149 rd_cfg.size = sizeof(regs->statistic); in vdpu382_h264d_start()
1150 rd_cfg.offset = OFFSET_STATISTIC_REGS; in vdpu382_h264d_start()
1152 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); in vdpu382_h264d_start()
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu1_v2.c589 MppDevRegRdCfg rd_cfg; in hal_h264e_vepu1_start_v2() local
603 rd_cfg.reg = &ctx->regs_get; in hal_h264e_vepu1_start_v2()
604 rd_cfg.size = reg_size; in hal_h264e_vepu1_start_v2()
605 rd_cfg.offset = 0; in hal_h264e_vepu1_start_v2()
607 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h264e_vepu1_start_v2()
H A Dhal_h264e_vepu2_v2.c654 MppDevRegRdCfg rd_cfg; in hal_h264e_vepu2_start_v2() local
668 rd_cfg.reg = &ctx->regs_get; in hal_h264e_vepu2_start_v2()
669 rd_cfg.size = reg_size; in hal_h264e_vepu2_start_v2()
670 rd_cfg.offset = 0; in hal_h264e_vepu2_start_v2()
672 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h264e_vepu2_start_v2()
/rockchip-linux_mpp/mpp/hal/vpu/jpegd/
H A Dhal_jpegd_rkv.c678 MppDevRegRdCfg rd_cfg; in hal_jpegd_rkv_start() local
699 rd_cfg.reg = regs; in hal_jpegd_rkv_start()
700 rd_cfg.size = reg_size; in hal_jpegd_rkv_start()
701 rd_cfg.offset = 0; in hal_jpegd_rkv_start()
703 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_jpegd_rkv_start()
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c1670 MppDevRegRdCfg rd_cfg; in hal_h264e_vepu541_start() local
1695 rd_cfg.reg = &ctx->regs_ret.hw_status; in hal_h264e_vepu541_start()
1696 rd_cfg.size = sizeof(RK_U32); in hal_h264e_vepu541_start()
1697 rd_cfg.offset = VEPU541_REG_BASE_HW_STATUS; in hal_h264e_vepu541_start()
1699 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h264e_vepu541_start()
1705 rd_cfg.reg = &ctx->regs_ret.st_bsl; in hal_h264e_vepu541_start()
1706 rd_cfg.size = sizeof(ctx->regs_ret) - 4; in hal_h264e_vepu541_start()
1707 rd_cfg.offset = VEPU541_REG_BASE_STATISTICS; in hal_h264e_vepu541_start()
1709 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg); in hal_h264e_vepu541_start()

12