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Searched refs:MPP_ALIGN (Results 1 – 25 of 116) sorted by relevance

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/rockchip-linux_mpp/mpp/base/
H A Dmpp_sys_cfg.c235 case SYS_CFG_ALIGN_8: { return MPP_ALIGN(val, 8);}; in mpp_sys_cfg_align()
236 case SYS_CFG_ALIGN_16: { return MPP_ALIGN(val, 16);}; in mpp_sys_cfg_align()
237 case SYS_CFG_ALIGN_32: { return MPP_ALIGN(val, 32);}; in mpp_sys_cfg_align()
238 case SYS_CFG_ALIGN_64: { return MPP_ALIGN(val, 64);}; in mpp_sys_cfg_align()
239 case SYS_CFG_ALIGN_128: { return MPP_ALIGN(val, 128);}; in mpp_sys_cfg_align()
240 case SYS_CFG_ALIGN_256: { return MPP_ALIGN(val, 256);}; in mpp_sys_cfg_align()
241 case SYS_CFG_ALIGN_256_ODD: {return MPP_ALIGN(val, 256) | 256;}; in mpp_sys_cfg_align()
243 val = MPP_ALIGN(val, 64); in mpp_sys_cfg_align()
247 return ((MPP_ALIGN(val, 128) | 128) + 64); in mpp_sys_cfg_align()
249 case SYS_CFG_ALIGN_LEN_DEFAULT: { return (9 * MPP_ALIGN(val, 16) / 5);}; in mpp_sys_cfg_align()
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H A Dmpp_frame.c300 fbc_offset = MPP_ALIGN(MPP_ALIGN(p->width, 16) * in mpp_frame_get_fbc_offset()
301 MPP_ALIGN(p->height, 16) / 16, SZ_4K); in mpp_frame_get_fbc_offset()
319 return MPP_ALIGN(p->width, 16); in mpp_frame_get_fbc_stride()
/rockchip-linux_mpp/mpp/hal/rkdec/
H A Dvdpu382_com.c48 buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE); in update_size_offset()
210 (MPP_ALIGN(img_width, 256) | 256) : in vdpu382_afbc_align_calc()
211 (MPP_ALIGN(img_width, 64)); in vdpu382_afbc_align_calc()
229 RK_U32 down_scale_ver = MPP_ALIGN(ver_stride >> 1, 16); in vdpu382_setup_down_scale()
230 RK_U32 down_scale_hor = MPP_ALIGN(hor_stride >> 1, 16); in vdpu382_setup_down_scale()
246 com->reg030.y_scale_down_hor_stride = MPP_ALIGN(down_scale_hor, 16) >> 4; in vdpu382_setup_down_scale()
247 com->reg031.uv_scale_down_hor_stride = MPP_ALIGN(down_scale_hor, 16) >> 4; in vdpu382_setup_down_scale()
249 down_scale_y_offset = MPP_ALIGN(down_scale_y_offset, 16); in vdpu382_setup_down_scale()
266 RK_U32 seg_cnt_w = MPP_ALIGN(width, segment_w) / segment_w; in vdpu382_get_colmv_size()
267 RK_U32 seg_cnt_h = MPP_ALIGN(height, segment_h) / segment_h; in vdpu382_get_colmv_size()
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H A Dvdpu34x_com.c48 buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE); in update_size_offset()
215 (MPP_ALIGN(img_width, 256) | 256) : in vdpu34x_afbc_align_calc()
216 (MPP_ALIGN(img_width, 64)); in vdpu34x_afbc_align_calc()
238 RK_U32 seg_cnt_w = MPP_ALIGN(width, segment_w) / segment_w; in vdpu34x_get_colmv_size()
239 RK_U32 seg_cnt_h = MPP_ALIGN(height, segment_h) / segment_h; in vdpu34x_get_colmv_size()
240 RK_U32 seg_head_size = MPP_ALIGN(seg_cnt_w, 16) * seg_cnt_h; in vdpu34x_get_colmv_size()
245 RK_U32 colmv_block_size_w = MPP_ALIGN(width, 64) / colmv_size; in vdpu34x_get_colmv_size()
246 RK_U32 colmv_block_size_h = MPP_ALIGN(height, 64) / colmv_size; in vdpu34x_get_colmv_size()
251 return MPP_ALIGN(colmv_total_size, 128); in vdpu34x_get_colmv_size()
H A Dvdpu384a_com.c38 buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE); in update_size_offset()
70 mpp_assert(info[i].size < (RK_S32)MPP_ALIGN(width * rcb_coeff[i], RCB_ALLINE_SIZE)); in vdpu384a_check_rcb_buf_size()
73 mpp_assert(info[i].size < (RK_S32)MPP_ALIGN(height * rcb_coeff[i], RCB_ALLINE_SIZE)); in vdpu384a_check_rcb_buf_size()
146 (MPP_ALIGN(img_width, 256) | 256) : in vdpu384a_afbc_align_calc()
147 (MPP_ALIGN(img_width, 64)); in vdpu384a_afbc_align_calc()
228 RK_U32 down_scale_ver = MPP_ALIGN(down_scale_height, 16); in vdpu384a_update_thumbnail_frame_info()
229 RK_U32 down_scale_hor = MPP_ALIGN(down_scale_width, 16); in vdpu384a_update_thumbnail_frame_info()
253 RK_U32 down_scale_ver = MPP_ALIGN(down_scale_height, 16); in vdpu384a_setup_down_scale()
254 RK_U32 down_scale_hor = MPP_ALIGN(down_scale_width, 16); in vdpu384a_setup_down_scale()
293 downscale_buf_size = MPP_ALIGN(downscale_buf_size, 16); in vdpu384a_setup_down_scale()
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H A Dvdpu383_com.c37 buf_size = 2 * MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE); in update_size_offset()
134 (MPP_ALIGN(img_width, 256) | 256) : in vdpu383_afbc_align_calc()
135 (MPP_ALIGN(img_width, 64)); in vdpu383_afbc_align_calc()
216 RK_U32 down_scale_ver = MPP_ALIGN(down_scale_height, 16); in vdpu383_update_thumbnail_frame_info()
217 RK_U32 down_scale_hor = MPP_ALIGN(down_scale_width, 16); in vdpu383_update_thumbnail_frame_info()
241 RK_U32 down_scale_ver = MPP_ALIGN(down_scale_height, 16); in vdpu383_setup_down_scale()
242 RK_U32 down_scale_hor = MPP_ALIGN(down_scale_width, 16); in vdpu383_setup_down_scale()
281 downscale_buf_size = MPP_ALIGN(downscale_buf_size, 16); in vdpu383_setup_down_scale()
283 down_scale_y_offset = MPP_ALIGN((mpp_frame_get_buf_size(frame) - downscale_buf_size), 16); in vdpu383_setup_down_scale()
/rockchip-linux_mpp/osal/
H A Dmpp_common.c103 return MPP_ALIGN(val, 16); in mpp_align_16()
108 return MPP_ALIGN(val, 64); in mpp_align_64()
113 return MPP_ALIGN(val, 128); in mpp_align_128()
118 return MPP_ALIGN(val, 256) | 256; in mpp_align_256_odd()
123 val = MPP_ALIGN(val, 64); in mpp_align_128_odd_plus_64()
127 return ((MPP_ALIGN(val, 128) | 128) + 64); in mpp_align_128_odd_plus_64()
/rockchip-linux_mpp/utils/
H A Dmpp_enc_roi_utils.c193 RK_S32 mb_w = MPP_ALIGN(w, 64) / 64; in vepu54x_h265_set_roi()
194 RK_S32 mb_h = MPP_ALIGN(h, 64) / 64; in vepu54x_h265_set_roi()
226 RK_S32 mb_w = MPP_ALIGN(ctx->w, 16) / 16; in gen_vepu54x_roi()
227 RK_S32 mb_h = MPP_ALIGN(ctx->h, 16) / 16; in gen_vepu54x_roi()
228 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in gen_vepu54x_roi()
229 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in gen_vepu54x_roi()
463 RK_S32 mb_w = MPP_ALIGN(ctx->w, 16) / 16; in gen_vepu580_roi_h264()
464 RK_S32 mb_h = MPP_ALIGN(ctx->h, 16) / 16; in gen_vepu580_roi_h264()
465 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in gen_vepu580_roi_h264()
466 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in gen_vepu580_roi_h264()
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H A Dmpi_enc_utils.c42 stride = MPP_ALIGN(width, 8); in mpi_enc_width_default_stride()
46 stride = MPP_ALIGN(width, 16); in mpi_enc_width_default_stride()
52 stride = MPP_ALIGN(width, 8); in mpi_enc_width_default_stride()
56 stride = MPP_ALIGN(width, 8); in mpi_enc_width_default_stride()
69 stride = MPP_ALIGN(width, 8) * 2; in mpi_enc_width_default_stride()
74 stride = MPP_ALIGN(width, 8) * 3; in mpi_enc_width_default_stride()
83 stride = MPP_ALIGN(width, 8) * 4; in mpi_enc_width_default_stride()
873 cmd->ver_stride = MPP_ALIGN(cmd->height, 2); in mpi_enc_test_cmd_update_by_args()
1202 RK_U32 mb_w_max = MPP_ALIGN(width, 16) / 16; in mpi_enc_gen_osd_data()
1203 RK_U32 mb_h_max = MPP_ALIGN(height, 16) / 16; in mpi_enc_gen_osd_data()
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/rockchip-linux_mpp/test/
H A Dmpi_enc_test.c212 (MPP_ALIGN(w, 32) >> 5) * (MPP_ALIGN(h, 32) >> 5) * 20 : in get_mdinfo_size()
213 (MPP_ALIGN(w, 64) >> 6) * (MPP_ALIGN(h, 16) >> 4) * 16; in get_mdinfo_size()
215 md_size = (MPP_ALIGN(w, 64) >> 6) * (MPP_ALIGN(h, 64) >> 6) * 32; in get_mdinfo_size()
218 (MPP_ALIGN(w, 32) >> 5) * (MPP_ALIGN(h, 32) >> 5) * 16 : in get_mdinfo_size()
219 (MPP_ALIGN(w, 64) >> 6) * (MPP_ALIGN(h, 16) >> 4) * 16; in get_mdinfo_size()
276 (MPP_ALIGN(cmd->width, 16)); in test_ctx_init()
278 (MPP_ALIGN(cmd->height, 16)); in test_ctx_init()
346 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 3 / 2; in test_ctx_init()
355 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 2; in test_ctx_init()
372 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64); in test_ctx_init()
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H A Dmpi_enc_mt_test.c154 (MPP_ALIGN(cmd->width, 16)); in mt_test_ctx_init()
156 (MPP_ALIGN(cmd->height, 16)); in mt_test_ctx_init()
215 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 3 / 2; in mt_test_ctx_init()
224 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 2; in mt_test_ctx_init()
241 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64); in mt_test_ctx_init()
245 p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 4; in mt_test_ctx_init()
250 p->header_size = MPP_ALIGN(MPP_ALIGN(p->width, 16) * MPP_ALIGN(p->height, 16) / 16, SZ_4K); in mt_test_ctx_init()
817 region->x = MPP_ALIGN(p->width / 8, 16); in enc_test_input()
818 region->y = MPP_ALIGN(p->height / 8, 16); in enc_test_input()
827 region->x = MPP_ALIGN(p->width / 2, 16); in enc_test_input()
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/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu510_common.c65 reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4; in vepu510_set_roi()
66 reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4; in vepu510_set_roi()
67 reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4; in vepu510_set_roi()
68 reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4; in vepu510_set_roi()
H A Dvepu541_common.c29 RK_S32 stride_h = MPP_ALIGN(w, 64) / 16; in vepu541_get_roi_buf_size()
30 RK_S32 stride_v = MPP_ALIGN(h, 64) / 16; in vepu541_get_roi_buf_size()
40 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu541_set_one_roi()
41 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu541_set_one_roi()
42 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu541_set_one_roi()
95 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu541_set_roi()
96 RK_S32 mb_h = MPP_ALIGN(h, 16) / 16; in vepu541_set_roi()
97 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu541_set_roi()
98 RK_S32 stride_v = MPP_ALIGN(mb_h, 4); in vepu541_set_roi()
H A Dvepu511_common.c146 reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4; in vepu511_set_roi()
147 reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4; in vepu511_set_roi()
148 reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4; in vepu511_set_roi()
149 reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4; in vepu511_set_roi()
H A Dvepu540c_common.c78 reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4; in vepu540c_set_roi()
79 reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4; in vepu540c_set_roi()
80 reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4; in vepu540c_set_roi()
81 reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4; in vepu540c_set_roi()
/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_base.c29 return MPP_ALIGN(val, 16); in avsd_ver_align()
34 return MPP_ALIGN(val, 16); in avsd_hor_align()
39 return (2 * MPP_ALIGN(val, 16)); in avsd_len_align()
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu_v2.c227 RK_S32 aligned_w = MPP_ALIGN(w, 16); in h264e_vepu_buf_set_frame_size()
228 RK_S32 aligned_h = MPP_ALIGN(h, 16); in h264e_vepu_buf_set_frame_size()
256 bufs->nal_tab_size = MPP_ALIGN((bufs->mb_h + 1) * sizeof(RK_U32), 8); in h264e_vepu_buf_set_frame_size()
413 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
414 prep->size_c = hor_stride / 2 * MPP_ALIGN(prep->src_h / 2, 8); in h264e_vepu_prep_setup()
419 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
420 prep->size_c = hor_stride / 2 * MPP_ALIGN(prep->src_h / 2, 8); in h264e_vepu_prep_setup()
424 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
433 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
442 prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16); in h264e_vepu_prep_setup()
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/rockchip-linux_mpp/mpp/vproc/rga/test/
H A Drga_test.c234 mpp_frame_set_hor_stride(src_frm, MPP_ALIGN(src_w, 16)); in main()
235 mpp_frame_set_ver_stride(src_frm, MPP_ALIGN(src_h, 16)); in main()
241 mpp_frame_set_hor_stride(dst_frm, MPP_ALIGN(dst_w, 16)); in main()
242 mpp_frame_set_ver_stride(dst_frm, MPP_ALIGN(dst_h, 16)); in main()
280 mpp_frame_set_hor_stride(src_frm, MPP_ALIGN(dst_w, 16) * 2); in main()
281 mpp_frame_set_ver_stride(src_frm, MPP_ALIGN(src_h, 16) / 2); in main()
/rockchip-linux_mpp/mpp/hal/rkdec/av1d/
H A Dhal_av1d_vdpu383.c24 #define VDPU383_UNCMPS_HEADER_SIZE (MPP_ALIGN(5159, 128) / 8) // byte, 5159 bit
27 #define VDPU383_RCB_STRMD_ROW_LEN (MPP_ALIGN(dxva->width, 8) / 8 * 100)
28 #define VDPU383_RCB_STRMD_TILE_ROW_LEN (MPP_ALIGN(dxva->width, 8) / 8 * 100)
29 #define VDPU383_RCB_INTER_ROW_LEN (MPP_ALIGN(dxva->width, 64) / 64 * 2752)
30 #define VDPU383_RCB_INTER_TILE_ROW_LEN (MPP_ALIGN(dxva->width, 64) / 64 * 2752)
31 #define VDPU383_RCB_INTRA_ROW_LEN (MPP_ALIGN(dxva->width, 512) * 12 * 3)
32 #define VDPU383_RCB_INTRA_TILE_ROW_LEN (MPP_ALIGN(dxva->width, 512) * 12 * 3)
33 #define VDPU383_RCB_FILTERD_ROW_LEN (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
34 #define VDPU383_RCB_FILTERD_PROTECT_ROW_LEN (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
35 #define VDPU383_RCB_FILTERD_TILE_ROW_LEN (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
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/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu383.c31 #define VDPU383_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU383_CABAC_TAB_SIZE, SZ_4K))
33 #define VDPU383_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU383_SPSPPS_SIZE, SZ_4K))
34 #define VDPU383_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU383_RPS_SIZE, SZ_4K))
35 #define VDPU383_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU383_SCALING_LIST_SIZE, SZ_4K))
48 #define VDPU383_SPS_PPS_LEN (MPP_ALIGN(1338, 128) / 8) // byte, 1338 bit
117 return MPP_ALIGN(val, 16); in rkv_ver_align()
122 return (2 * MPP_ALIGN(val, 16)); in rkv_len_align()
127 return ((5 * MPP_ALIGN(val, 16)) / 2); in rkv_len_align_422()
443 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in set_registers()
740 width = MPP_ALIGN(width, H264_CTU_SIZE); in h264d_refine_rcb_size()
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H A Dhal_h264d_vdpu34x.c46 #define VDPU34X_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_CABAC_TAB_SIZE, SZ_4K))
48 #define VDPU34X_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_SPSPPS_SIZE, SZ_4K))
49 #define VDPU34X_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_RPS_SIZE, SZ_4K))
50 #define VDPU34X_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU34X_SCALING_LIST_SIZE, SZ_4K))
327 return MPP_ALIGN(val, 16); in rkv_ver_align()
332 return MPP_ALIGN(val, 16); in rkv_hor_align()
337 return (MPP_ALIGN(val, 256) | 256); in rkv_hor_align_256_odds()
342 return (2 * MPP_ALIGN(val, 16)); in rkv_len_align()
347 return ((5 * MPP_ALIGN(val, 16)) / 2); in rkv_len_align_422()
559 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
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H A Dhal_h264d_vdpu384a.c24 #define VDPU384A_SPSPPS_SIZE (MPP_ALIGN(2266 + 64, 128) / 8) /* byte, 2266 bit + Reserve 64…
30 #define VDPU384A_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU384A_SPSPPS_SIZE, SZ_4K))
31 #define VDPU384A_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU384A_SCALING_LIST_SIZE, SZ_4K))
104 return MPP_ALIGN(val, 16); in rkv_ver_align()
109 return (MPP_ALIGN(val, 16) * 3 / 2); in rkv_len_align()
114 return ((5 * MPP_ALIGN(val, 16)) / 2); in rkv_len_align_422()
379 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in set_registers()
691 width = MPP_ALIGN(width, H264_CTU_SIZE); in h264d_refine_rcb_size()
692 height = MPP_ALIGN(height, H264_CTU_SIZE); in h264d_refine_rcb_size()
705 rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2) * (mbaff ? 2 : 1); in h264d_refine_rcb_size()
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/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu510_tune.c158 RK_S32 w32 = MPP_ALIGN(ctx->cfg->prep.width, 32); in vepu510_h265e_tune_qpmap_init()
159 RK_S32 h32 = MPP_ALIGN(ctx->cfg->prep.height, 32); in vepu510_h265e_tune_qpmap_init()
246 RK_S32 w32 = MPP_ALIGN(cfg->prep.width, 32); in vepu510_h265e_tune_stat_update()
247 RK_S32 h32 = MPP_ALIGN(cfg->prep.height, 32); in vepu510_h265e_tune_stat_update()
248 RK_U32 b16_num = MPP_ALIGN(cfg->prep.width, 16) * MPP_ALIGN(cfg->prep.height, 16) / 256; in vepu510_h265e_tune_stat_update()
/rockchip-linux_mpp/mpp/legacy/
H A Dvpu_api_legacy.cpp143 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
149 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 2 * MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
153 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 3 * MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
159 mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 4 * MPP_ALIGN(width, 16)); in vpu_api_set_enc_cfg()
165 mpp_enc_cfg_set_s32(enc_cfg, "prep:ver_stride", MPP_ALIGN(height, 8)); in vpu_api_set_enc_cfg()
242 RK_U32 hor_stride = MPP_ALIGN(width, 16); in copy_align_raw_buffer_to_dest()
243 RK_U32 ver_stride = MPP_ALIGN(height, 8); in copy_align_raw_buffer_to_dest()
709 RK_U32 hor_stride = MPP_ALIGN(width, 16); in decode()
710 RK_U32 ver_stride = MPP_ALIGN(height, 16); in decode()
1080 RK_U32 hor_stride = MPP_ALIGN(width, 16); in encode()
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/rockchip-linux_mpp/mpp/hal/vpu/av1d/
H A Dhal_av1d_vdpu.c113 return MPP_ALIGN(val, 8); in rkv_ver_align()
118 return MPP_ALIGN(val, 16); in rkv_hor_align()
123 return (2 * MPP_ALIGN(val, 128)); in rkv_len_align()
128 return ((5 * MPP_ALIGN(val, 64)) / 2); in rkv_len_align_422()
152 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_base, MPP_ALIGN(sizeof(AV1CDFs)… in hal_av1d_alloc_res()
153 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_out_base, MPP_ALIGN(sizeof(AV1C… in hal_av1d_alloc_res()
155 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->film_grain_mem, MPP_ALIGN(sizeof(AV1Film… in hal_av1d_alloc_res()
156 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->global_model, MPP_ALIGN(GLOBAL_MODEL_SIZ… in hal_av1d_alloc_res()
157 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->tile_buf, MPP_ALIGN(32 * MaxTiles, 4096)… in hal_av1d_alloc_res()
173 RK_U32 pic_height = MPP_ALIGN(dxva->height, 64); in vdpu_av1d_filtermem_alloc()
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