24 #define VDPU383_UNCMPS_HEADER_SIZE            (MPP_ALIGN(5159, 128) / 8) // byte, 5159 bit
27 #define VDPU383_RCB_STRMD_ROW_LEN             (MPP_ALIGN(dxva->width, 8) / 8 * 100)
28 #define VDPU383_RCB_STRMD_TILE_ROW_LEN        (MPP_ALIGN(dxva->width, 8) / 8 * 100)
29 #define VDPU383_RCB_INTER_ROW_LEN             (MPP_ALIGN(dxva->width, 64) / 64 * 2752)
30 #define VDPU383_RCB_INTER_TILE_ROW_LEN        (MPP_ALIGN(dxva->width, 64) / 64 * 2752)
31 #define VDPU383_RCB_INTRA_ROW_LEN             (MPP_ALIGN(dxva->width, 512) * 12 * 3)
32 #define VDPU383_RCB_INTRA_TILE_ROW_LEN        (MPP_ALIGN(dxva->width, 512) * 12 * 3)
33 #define VDPU383_RCB_FILTERD_ROW_LEN           (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
34 #define VDPU383_RCB_FILTERD_PROTECT_ROW_LEN   (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
35 #define VDPU383_RCB_FILTERD_TILE_ROW_LEN      (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
36 #define VDPU383_RCB_FILTERD_TILE_COL_LEN      (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 7 * 3 …
37 #define VDPU383_RCB_FILTERD_AV1_UP_TL_COL_LEN (MPP_ALIGN(dxva->width, 64) * 10 * 22)
1254     return MPP_ALIGN(val, 8);  in rkv_ver_align()
1259     return (2 * MPP_ALIGN(val, 128));  in rkv_len_align()
1264     return ((5 * MPP_ALIGN(val, 64)) / 2);  in rkv_len_align_422()
1307 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs, MPP_ALIGN(VDPU383_INFO_BUF_SIZE(ma…  in hal_av1d_alloc_res()
1324 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->cdf_rd_def_base, 200 * MPP_ALIGN(sizeof(…  in hal_av1d_alloc_res()
1545         RK_U32 mi_rows = MPP_ALIGN(dxva->width, 8) >> MI_SIZE_LOG2;  in prepare_uncompress_header()
1546         RK_U32 mi_cols = MPP_ALIGN(dxva->height, 8) >> MI_SIZE_LOG2;  in prepare_uncompress_header()
1548         RK_U32 prev_mi_rows = MPP_ALIGN(dxva->frame_refs[0].width, 8) >> MI_SIZE_LOG2;  in prepare_uncompress_header()
1549         RK_U32 prev_mi_cols = MPP_ALIGN(dxva->frame_refs[0].height, 8) >> MI_SIZE_LOG2;  in prepare_uncompress_header()
1867     width = MPP_ALIGN(width, sb_size);  in av1d_refine_rcb_size()
1868     height = MPP_ALIGN(height, sb_size);  in av1d_refine_rcb_size()
1884     rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2);  in av1d_refine_rcb_size()
1896     rcb_bits = (RK_U32)(MPP_ALIGN(width, 64) * (32 * bit_depth + 10));  in av1d_refine_rcb_size()
1907         rcb_bits = (MPP_ALIGN(height, 64) * (101 * bit_depth + 32)) + ext_col_align_size;  in av1d_refine_rcb_size()
1996     mv_size = MPP_ALIGN(dxva->width, 64) / 64 * MPP_ALIGN(dxva->height, 64) / 64 * 1024;  in vdpu383_av1d_colmv_setup()
2022     size_t segid_size = (MPP_ALIGN(dxva->width, 128) / 128) * \  in vdpu383_av1d_cdf_setup()
2023                         (MPP_ALIGN(dxva->height, 128) / 128) * \  in vdpu383_av1d_cdf_setup()
2294         regs->av1d_paras.reg66_stream_len = MPP_ALIGN(p_hal->strm_len + 15, 128);  in vdpu383_av1d_gen_regs()
2342                 RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64);  in vdpu383_av1d_gen_regs()
2350                 regs->av1d_paras.reg68_hor_virstride = MPP_ALIGN(hor_virstride * 6, 16) >> 4;  in vdpu383_av1d_gen_regs()
2375                         hor_virstride = MPP_ALIGN(hor_virstride * 6, 16);  in vdpu383_av1d_gen_regs()