rkdec/h264d/hal_h264d_vdpu384a.c

24 #define VDPU384A_SPSPPS_SIZE         (MPP_ALIGN(2266 + 64, 128) / 8) /* byte, 2266 bit + Reserve 64…
30 #define VDPU384A_SPSPPS_ALIGNED_SIZE         (MPP_ALIGN(VDPU384A_SPSPPS_SIZE, SZ_4K))
31 #define VDPU384A_SCALING_LIST_ALIGNED_SIZE   (MPP_ALIGN(VDPU384A_SCALING_LIST_SIZE, SZ_4K))
104     return MPP_ALIGN(val, 16);  in rkv_ver_align()
109     return (MPP_ALIGN(val, 16) * 3 / 2);  in rkv_len_align()
114     return ((5 * MPP_ALIGN(val, 16)) / 2);  in rkv_len_align_422()
379             fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16;  in set_registers()
691     width = MPP_ALIGN(width, H264_CTU_SIZE);  in h264d_refine_rcb_size()
692     height = MPP_ALIGN(height, H264_CTU_SIZE);  in h264d_refine_rcb_size()
705     rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2) * (mbaff ? 2 : 1);  in h264d_refine_rcb_size()
732     RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);  in hal_h264d_rcb_info_update()
733     RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);  in hal_h264d_rcb_info_update()
768     RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);  in vdpu384a_h264d_gen_regs()
769     RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);  in vdpu384a_h264d_gen_regs()
773     RK_S32 mv_size = MPP_ALIGN(width, 64) * MPP_ALIGN(height, 16); // 16 byte unit  in vdpu384a_h264d_gen_regs()