113     return MPP_ALIGN(val, 8);  in rkv_ver_align()
118     return MPP_ALIGN(val, 16);  in rkv_hor_align()
123     return (2 * MPP_ALIGN(val, 128));  in rkv_len_align()
128     return ((5 * MPP_ALIGN(val, 64)) / 2);  in rkv_len_align_422()
152 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_base, MPP_ALIGN(sizeof(AV1CDFs)…  in hal_av1d_alloc_res()
153 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->prob_tbl_out_base, MPP_ALIGN(sizeof(AV1C…  in hal_av1d_alloc_res()
155 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->film_grain_mem, MPP_ALIGN(sizeof(AV1Film…  in hal_av1d_alloc_res()
156 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->global_model, MPP_ALIGN(GLOBAL_MODEL_SIZ…  in hal_av1d_alloc_res()
157 …BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->tile_buf, MPP_ALIGN(32 * MaxTiles, 4096)…  in hal_av1d_alloc_res()
173     RK_U32 pic_height = MPP_ALIGN(dxva->height, 64);  in vdpu_av1d_filtermem_alloc()
187     filt_info[DB_DATA_COL].size = MPP_ALIGN(pic_height * 12 * max_bit_depth / 8, 128);  in vdpu_av1d_filtermem_alloc()
193     filt_info[DB_CTRL_COL].size = MPP_ALIGN(pic_height * 2 * 16 / 4, 128);  in vdpu_av1d_filtermem_alloc()
201     filt_info[CDEF_COL].size = MPP_ALIGN(height_in_sb * 44 * max_bit_depth * 16 / 8, 128);  in vdpu_av1d_filtermem_alloc()
209     filt_info[SR_COL].size = MPP_ALIGN(height_in_sb * (3040 + 1280), 128);  in vdpu_av1d_filtermem_alloc()
217     filt_info[LR_COL].size = MPP_ALIGN(stripe_num * 1536 * max_bit_depth / 8, 128);  in vdpu_av1d_filtermem_alloc()
226     if (!mpp_buffer_get(p_hal->buf_group, &ctx->filter_mem, MPP_ALIGN(size, SZ_4K)))  in vdpu_av1d_filtermem_alloc()
1218     regs->swreg4.sw_pic_width_in_cbs    = MPP_ALIGN(dxva->width, 8) >> 3;  in vdpu_av1d_set_picture_dimensions()
1219     regs->swreg4.sw_pic_height_in_cbs   = MPP_ALIGN(dxva->height, 8) >> 3;  in vdpu_av1d_set_picture_dimensions()
1220     regs->swreg12.sw_pic_width_pad    = MPP_ALIGN(dxva->width, 8) - dxva->width;  in vdpu_av1d_set_picture_dimensions()
1221     regs->swreg12.sw_pic_height_pad   = MPP_ALIGN(dxva->height, 8) - dxva->height;  in vdpu_av1d_set_picture_dimensions()
1822     RK_U32 out_w = MPP_ALIGN(dxva->max_width * dxva->bitdepth, 16 * 8) / 8;  in vdpu_av1d_setup_tile_bufs()
1823 …RK_U32 num_sbs = (MPP_ALIGN(dxva->max_width, 64) / 64 + 1) * (MPP_ALIGN(dxva->max_height, 64) / 64…  in vdpu_av1d_setup_tile_bufs()
1824     RK_U32 dir_mvs_size = MPP_ALIGN(num_sbs * 24 * 128 / 8, 16) * 2;  in vdpu_av1d_setup_tile_bufs()
1825     RK_U32 out_h = MPP_ALIGN(dxva->max_height, 16);  in vdpu_av1d_setup_tile_bufs()
1994         size = MPP_ALIGN(GLOBAL_MODEL_SIZE, 2048);  in vdpu_av1d_gen_regs()
2014         size = MPP_ALIGN(p_hal->strm_len, 1);  in vdpu_av1d_gen_regs()
2023         size = MPP_ALIGN(sizeof(AV1FilmGrainMemory), 2048);  in vdpu_av1d_gen_regs()
2033         size = MPP_ALIGN(sizeof(AV1CDFs), 2048);  in vdpu_av1d_gen_regs()
2043         size = MPP_ALIGN(sizeof(AV1CDFs), 2048);  in vdpu_av1d_gen_regs()
2125         regs->swreg258.sw_strm_buffer_len = MPP_ALIGN(p_hal->strm_len, 128);//  in vdpu_av1d_gen_regs()
2127         regs->swreg6.sw_stream_len  = MPP_ALIGN(p_hal->strm_len, 128);//p_hal->strm_len - offset;  in vdpu_av1d_gen_regs()