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/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dcache.S31 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
32 add x2, x2, #4 /* x2 <- log2(cache line size) */
49 lsl x7, x4, x2
138 mov x2, #4
139 lsl x2, x2, x3 /* cache line size */
142 sub x3, x2, #1
145 add x0, x0, x2
165 mov x2, #4
166 lsl x2, x2, x3 /* cache line size */
169 sub x3, x2, #1
[all …]
H A Dexceptions.S87 stp x1, x2, [sp, #-16]!
92 mrs x2, elr_el3
102 mrs x2, elr_el2
113 mrs x2, elr_el1
122 stp x2, x0, [sp, #-16]!
133 ldp x2, x0, [sp],#16
135 3: msr elr_el3, x2
137 2: msr elr_el2, x2
139 1: msr elr_el1, x2
141 ldp x1, x2, [sp],#16
H A Dsleep.S93 stp x2, x3, [sp, #-88]!
106 mrs x2, vbar_el2
116 stp x2, x3, [x0, #0]
128 ldp x2, x3, [sp], #88
138 ldr x2, [x1]
141 add x2, x2, #PM_CTX_PHYS
142 ldr x0, [x2]
164 ldp x2, x3, [x0]
172 msr vbar_el2, x2
H A Dsec_firmware_asm.S34 str w3, [x2]
48 mov x2, 0x0
69 mov x3, x2
70 mov x2, x1
H A Dstart.S74 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
77 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
78 ldr x4, [x2], #8 /* x4 <- addend */
86 cmp x2, x3
128 switch_el x2, 3f, 2f, 1f
/rk3399_rockchip-uboot/arch/arm/lib/
H A Drelocate_64.S49 adrp x2, __image_copy_end /* x2 <- address bits [31:12] */
50 add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */
54 cmp x1, x2 /* until source end address [x2] */
61 adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */
62 add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */
66 ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */
67 ldr x4, [x2], #8 /* x4 <- addend */
77 cmp x2, x3
H A Dsetjmp_aarch64.S20 mov x2, sp
21 str x2, [x0, #96]
35 ldr x2, [x0,#96]
36 mov sp, x2
H A Dccn504.S30 str x9, [x0, x2]
31 1: ldr x10, [x0, x2]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S37 ldr x2, =DCFG_CCSR_SVR
38 ldr w2, [x2]
47 ldr x2, =SCFG_GIC400_ALIGN
48 ldr w2, [x2]
110 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
314 mov x2, #0
316 str x2, [x0]
353 ldr x2, [x0]
354 cmp x2, x1 /* check status */
377 ldr x2, [x0]
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3288-fennec.dts20 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
23 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
26 0x0 0xc3 0x6 0x2>;
H A Drk3288-evb.dts37 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
40 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
43 0x0 0xc3 0x6 0x2>;
H A Drk3288-tinker.dts20 rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
23 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
26 0x0 0xc3 0x6 0x2>;
H A Darmada-7040-db-nand.dts116 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
117 0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
119 0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
H A Dimx53-cx9020.dts12 #define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0
13 #define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0
14 #define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0
15 #define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0
H A Dfsl-ls1043a-qds.dtsi95 reg = <0x2>;
139 0x2 0x0 0x0 0x7fb00000 0x00000100>;
162 reg = <0x2 0x0 0x0000100>;
H A Dls1021a-qds.dtsi76 reg = <0x2>;
119 0x2 0x0 0x7e800000 0x00010000
164 reg = <0x2>;
H A Dfsl-ls1043a-rdb.dts73 0x2 0x0 0x0 0x7fb00000 0x00000100>;
93 reg = <0x2 0x0 0x0000100>;
H A Darmada-380.dtsi92 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
93 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
123 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
124 0x81000000 0 0 0x81000000 0x2 0 1 0>;
/rk3399_rockchip-uboot/drivers/rknand/
H A Drk_ftl_arm_v8.S20 add x2, x1, x0
24 ldrb w19, [x2, 8]
53 adrp x2, .LANCHOR1
55 ldr x3, [x2, #:lo12:.LANCHOR1]
101 adrp x2, .LANCHOR3
104 ldrb w2, [x2, #:lo12:.LANCHOR3]
122 adrp x2, .LANCHOR5
123 add x2, x2, :lo12:.LANCHOR5
124 ldrh w4, [x2, x3, lsl 1]
125 adrp x2, .LANCHOR6
[all …]
H A Drk_zftl_arm_v8.S38 adrp x2, .LANCHOR1
41 ldrb w1, [x2, #:lo12:.LANCHOR1]
45 ldrb w2, [x2, #:lo12:.LANCHOR1]
54 adrp x2, .LANCHOR3
55 add x2, x2, :lo12:.LANCHOR3
56 ldrh w0, [x2, w0, uxtw 1]
88 mov x23, x2
157 adrp x2, .LANCHOR6
161 ldr x2, [x2, #:lo12:.LANCHOR6]
165 add x21, x2, 112
[all …]
H A Drk_zftl_spl_arm_v8.S38 adrp x2, .LANCHOR1
41 ldrb w1, [x2, #:lo12:.LANCHOR1]
45 ldrb w2, [x2, #:lo12:.LANCHOR1]
54 adrp x2, .LANCHOR3
55 add x2, x2, :lo12:.LANCHOR3
56 ldrh w0, [x2, w0, uxtw 1]
88 mov x23, x2
157 adrp x2, .LANCHOR6
161 ldr x2, [x2, #:lo12:.LANCHOR6]
165 add x21, x2, 112
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dlowlevel_init.S29 mov x3, x2
30 mov x2, x1
/rk3399_rockchip-uboot/drivers/rkflash/
H A Drk_sftl_arm_v8.S32 str w4, [x2]
68 adrp x2, .LANCHOR3
76 str w1, [x2, #:lo12:.LANCHOR3]
77 adrp x2, .LANCHOR5
78 ldrh w2, [x2, #:lo12:.LANCHOR5]
80 adrp x2, .LANCHOR4
81 strh w0, [x2, #:lo12:.LANCHOR4]
97 adrp x2, .LANCHOR10
111 strh w8, [x2, #:lo12:.LANCHOR10]
140 ldrh w0, [x2, #:lo12:.LANCHOR10]
[all …]
/rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rv1126/
H A Dsdram-rv1126-loader_params.inc125 ((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) |
127 (((0x2 << 6) | (0x1 << 4) | (0x3 << 2) | (0x0 << 0)) << 24),
130 (((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0)) << 16) |
131 (((0x3 << 6) | (0x0 << 4) | (0x2 << 2) | (0x1 << 0)) << 24),
/rk3399_rockchip-uboot/include/
H A Dvxworks.h33 u32 x2; /* don't care, used by VxWorks */ member

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