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Searched refs:writew (Results 1 – 25 of 92) sorted by relevance

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/rk3399_rockchip-uboot/board/renesas/sh7753evb/
H A Dsh7753evb.c28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0x0000, &gpio->pdcr); /* SPI0 */ in init_gpio()
32 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
33 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
34 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ in init_gpio()
35 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
36 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
37 writew(0x0000, &gpio->pjcr); /* SCIF4 */ in init_gpio()
[all …]
/rk3399_rockchip-uboot/board/renesas/sh7752evb/
H A Dsh7752evb.c28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
32 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
33 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
34 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
35 writew(0x0003, &gpio->pkcr); /* SerMux */ in init_gpio()
36 writew(0x0000, &gpio->plcr); /* SerMux */ in init_gpio()
37 writew(0x0000, &gpio->pmcr); /* RIIC */ in init_gpio()
[all …]
/rk3399_rockchip-uboot/drivers/i2c/
H A Dadi_i2c.c97 writew(XMTSERV, &twi->int_stat); in wait_for_completion()
99 writew(*(msg->abuf++), &twi->xmt_data8); in wait_for_completion()
102 writew(*(msg->buf++), &twi->xmt_data8); in wait_for_completion()
107 writew(ctl | RSTART | MDIR, in wait_for_completion()
110 writew(ctl | STOP, &twi->master_ctl); in wait_for_completion()
114 writew(RCVSERV, &twi->int_stat); in wait_for_completion()
120 writew(ctl | STOP, &twi->master_ctl); in wait_for_completion()
124 writew(MERR, &twi->int_stat); in wait_for_completion()
128 writew(MCOMP, &twi->int_stat); in wait_for_completion()
133 writew(ctl, &twi->master_ctl); in wait_for_completion()
[all …]
H A Domap24xx_i2c.c124 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
132 writew(stat, &i2c_base->stat);
141 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
175 writew(0xFFFF, &i2c_base->stat);
194 writew(I2C_STAT_RRDY, &i2c_base->stat);
254 writew(0, &i2c_base->con);
255 writew(psc, &i2c_base->psc);
256 writew(scll, &i2c_base->scll);
257 writew(sclh, &i2c_base->sclh);
258 writew(I2C_CON_EN, &i2c_base->con);
[all …]
/rk3399_rockchip-uboot/arch/x86/cpu/queensbay/
H A Dirq.c43 writew(PIRQE, &rcba->d02ir); in queensbay_irq_router_probe()
44 writew(PIRQF, &rcba->d03ir); in queensbay_irq_router_probe()
45 writew(PIRQG, &rcba->d27ir); in queensbay_irq_router_probe()
46 writew(PIRQH, &rcba->d31ir); in queensbay_irq_router_probe()
47 writew(PIRQA, &rcba->d23ir); in queensbay_irq_router_probe()
48 writew(PIRQB, &rcba->d24ir); in queensbay_irq_router_probe()
49 writew(PIRQC, &rcba->d25ir); in queensbay_irq_router_probe()
50 writew(PIRQD, &rcba->d26ir); in queensbay_irq_router_probe()
/rk3399_rockchip-uboot/board/renesas/sh7763rdp/
H A Dsh7763rdp.c40 writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); in board_init()
44 writew(((dat & ~0xff00) | 0x2400), PSEL1); in board_init()
45 writew(0, PFCR); in board_init()
46 writew(0, PGCR); in board_init()
47 writew(0, PHCR); in board_init()
/rk3399_rockchip-uboot/board/renesas/r7780mp/
H A Dr7780mp.c29 writew(0x0, PHCR); in board_init()
43 writew(0x432, FPGA_CFCTL); in ide_set_reset()
45 writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); in ide_set_reset()
47 writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); in ide_set_reset()
49 writew(0x01, FPGA_CFCDINTCLR); in ide_set_reset()
/rk3399_rockchip-uboot/drivers/watchdog/
H A Dimx_watchdog.c18 writew(0x5555, &wdog->wsr); in hw_watchdog_reset()
19 writew(0xaaaa, &wdog->wsr); in hw_watchdog_reset()
36 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | in hw_watchdog_init()
48 writew(0x5555, &wdog->wsr); in reset_cpu()
49 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ in reset_cpu()
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx27/
H A Dreset.c30 writew(0x0000, &regs->wcr); in reset_cpu()
33 writew(0x5555, &regs->wsr); in reset_cpu()
34 writew(0xAAAA, &regs->wsr); in reset_cpu()
37 writew(WCR_WDE, &regs->wcr); in reset_cpu()
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx25/
H A Dreset.c30 writew(0, &regs->wcr); in reset_cpu()
33 writew(WSR_UNLOCK1, &regs->wsr); in reset_cpu()
34 writew(WSR_UNLOCK2, &regs->wsr); in reset_cpu()
37 writew(WCR_WDE, &regs->wcr); in reset_cpu()
/rk3399_rockchip-uboot/drivers/usb/musb/
H A Dmusb_core.c28 writew(0, &musbr->intrtxe); in musb_start()
29 writew(0, &musbr->intrrxe); in musb_start()
53 writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
86 writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); in musb_configure_ep()
90 writew(csr | MUSB_TXCSR_FLUSHFIFO, in musb_configure_ep()
99 writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); in musb_configure_ep()
103 writew(csr | MUSB_RXCSR_FLUSHFIFO, in musb_configure_ep()
H A Dmusb_hcd.c50 writew(csr, &musbr->txcsr); in write_toggle()
53 writew(csr, &musbr->txcsr); in write_toggle()
55 writew(csr, &musbr->txcsr); in write_toggle()
64 writew(csr, &musbr->rxcsr); in write_toggle()
68 writew(csr, &musbr->rxcsr); in write_toggle()
70 writew(csr, &musbr->rxcsr); in write_toggle()
89 writew(csr, &musbr->txcsr); in check_stall()
97 writew(csr, &musbr->txcsr); in check_stall()
104 writew(csr, &musbr->rxcsr); in check_stall()
126 writew(csr, &musbr->txcsr); in wait_until_ep0_ready()
[all …]
H A Dmusb_udc.c214 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_stall()
225 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_ack_req()
234 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_ep0_tx_ready()
243 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_ep0_tx_ready_and_last()
252 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_last()
283 writew(peri_rxcsr, &musbr->ep[ep].epN.rxcsr); in musb_peri_rx_ack()
292 writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); in musb_peri_tx_ready()
606 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0()
611 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0()
822 writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); in udc_endpoint_write()
/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Dirq.c29 writew(PIRQC, &rcba->rmu_ir); in quark_irq_router_probe()
30 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), in quark_irq_router_probe()
32 writew(PIRQD, &rcba->core_ir); in quark_irq_router_probe()
33 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), in quark_irq_router_probe()
/rk3399_rockchip-uboot/arch/sh/lib/
H A Dtime_sh2.c24 writew(readw(CMSTR) | 0x01, CMSTR); in cmt_timer_start()
29 writew(readw(CMSTR) & ~0x01, CMSTR); in cmt_timer_stop()
37 writew(CMT_CMCSR_INIT, CMCSR_0); in timer_init()
41 writew(CMT_TIMER_RESET, CMCOR_0); in timer_init()
/rk3399_rockchip-uboot/board/ronetix/pm9263/
H A Dpm9263.c181 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
182 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ in pm9263_lcd_hw_psram_init()
187 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
189 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
196 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
197 writew(0x5678, PHYS_PSRAM + 2); in pm9263_lcd_hw_psram_init()
207 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
209 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
212 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
213 writew(0x5678, PHYS_PSRAM+2); in pm9263_lcd_hw_psram_init()
/rk3399_rockchip-uboot/board/ti/panda/
H A Dpanda.c82 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); in get_board_revision()
83 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); in get_board_revision()
94 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
96 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
98 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
112 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
147 writew((IEN | M3), in is_panda_es_rev_b3()
/rk3399_rockchip-uboot/board/renesas/sh7757lcr/
H A Dsh7757lcr.c93 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ in init_pcie_bridge()
94 writew(0x0000, &pciebrg->cp_ctrl); in init_pcie_bridge()
95 writew(0x0000, &pciebrg->cp_addr); in init_pcie_bridge()
99 writew(tmp, &pciebrg->cp_data); in init_pcie_bridge()
102 writew(0xa500, &pciebrg->ctrl_h8s); /* start */ in init_pcie_bridge()
117 writew(0x0100, &phy->reset); /* set reset */ in init_usb_phy()
119 writew(0x0002, &phy->portsel); in init_usb_phy()
121 writew(0x0111, &phy->reset); /* clear reset */ in init_usb_phy()
123 writew(0x4000, &common0->suspmode); in init_usb_phy()
124 writew(0x4000, &common1->suspmode); in init_usb_phy()
/rk3399_rockchip-uboot/board/compulab/common/
H A Domap3_smc911x.c39 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in cl_omap3_smc911x_setup_net_chip_gmpc()
42 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in cl_omap3_smc911x_setup_net_chip_gmpc()
45 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in cl_omap3_smc911x_setup_net_chip_gmpc()
/rk3399_rockchip-uboot/arch/arm/cpu/arm946es/
H A Dcpu.c60 writew(0x0, 0xfffece10); in reset_cpu()
61 writew(0x8, 0xfffece10); in reset_cpu()
/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dinit.c78 writew(enable, &wdog1->wmcr); in imx_set_wdog_powerdown()
79 writew(enable, &wdog2->wmcr); in imx_set_wdog_powerdown()
82 writew(enable, &wdog3->wmcr); in imx_set_wdog_powerdown()
84 writew(enable, &wdog4->wmcr); in imx_set_wdog_powerdown()
/rk3399_rockchip-uboot/board/freescale/mx31ads/
H A Dmx31ads.c69 writew(0x8023, CS4_BASE + 4); in board_early_init_f()
77 writew(0xDF, CS4_BASE + 6); in board_early_init_f()
/rk3399_rockchip-uboot/include/
H A Diotrace.h30 #undef writew
31 #define writew(val, addr) iotrace_writew(val, (const void *)(addr)) macro
/rk3399_rockchip-uboot/board/isee/igep00x0/
H A Digep00x0.c121 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
123 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
125 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
/rk3399_rockchip-uboot/arch/xtensa/include/asm/
H A Dio.h43 #define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b)) macro
50 #define __raw_writew writew
63 #define outw(val, port) writew((val), (u16 *)((unsigned long)(port)))

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