xref: /rk3399_rockchip-uboot/board/renesas/sh7763rdp/sh7763rdp.c (revision cdbb0cf8ecf30d5dbbfa500e8939a32ef45896c5)
178385bf2SNobuhiro Iwamatsu /*
278385bf2SNobuhiro Iwamatsu  * Copyright (C) 2008 Renesas Solutions Corp.
378385bf2SNobuhiro Iwamatsu  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
478385bf2SNobuhiro Iwamatsu  * Copyright (C) 2007 Kenati Technologies, Inc.
578385bf2SNobuhiro Iwamatsu  *
678385bf2SNobuhiro Iwamatsu  * board/sh7763rdp/sh7763rdp.c
778385bf2SNobuhiro Iwamatsu  *
8*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
978385bf2SNobuhiro Iwamatsu  */
1078385bf2SNobuhiro Iwamatsu 
1178385bf2SNobuhiro Iwamatsu #include <common.h>
1278385bf2SNobuhiro Iwamatsu #include <asm/io.h>
1378385bf2SNobuhiro Iwamatsu #include <asm/processor.h>
1478385bf2SNobuhiro Iwamatsu 
1578385bf2SNobuhiro Iwamatsu #define CPU_CMDREG	0xB1000006
1678385bf2SNobuhiro Iwamatsu #define PDCR        0xffef0006
1778385bf2SNobuhiro Iwamatsu #define PECR        0xffef0008
1878385bf2SNobuhiro Iwamatsu #define PFCR        0xffef000a
1978385bf2SNobuhiro Iwamatsu #define PGCR        0xffef000c
2078385bf2SNobuhiro Iwamatsu #define PHCR        0xffef000e
2178385bf2SNobuhiro Iwamatsu #define PJCR        0xffef0012
2278385bf2SNobuhiro Iwamatsu #define PKCR        0xffef0014
2378385bf2SNobuhiro Iwamatsu #define PLCR        0xffef0016
2478385bf2SNobuhiro Iwamatsu #define PMCR        0xffef0018
2578385bf2SNobuhiro Iwamatsu #define PSEL1       0xffef0072
2678385bf2SNobuhiro Iwamatsu #define PSEL2       0xffef0074
2778385bf2SNobuhiro Iwamatsu #define PSEL3       0xffef0076
2878385bf2SNobuhiro Iwamatsu 
checkboard(void)2978385bf2SNobuhiro Iwamatsu int checkboard(void)
3078385bf2SNobuhiro Iwamatsu {
3178385bf2SNobuhiro Iwamatsu 	puts("BOARD: Renesas SH7763 RDP\n");
3278385bf2SNobuhiro Iwamatsu 	return 0;
3378385bf2SNobuhiro Iwamatsu }
3478385bf2SNobuhiro Iwamatsu 
board_init(void)3578385bf2SNobuhiro Iwamatsu int board_init(void)
3678385bf2SNobuhiro Iwamatsu {
3778385bf2SNobuhiro Iwamatsu 	vu_short dat;
3878385bf2SNobuhiro Iwamatsu 
3978385bf2SNobuhiro Iwamatsu 	/* Enable mode */
4078385bf2SNobuhiro Iwamatsu 	writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
4178385bf2SNobuhiro Iwamatsu 
4278385bf2SNobuhiro Iwamatsu 	/* GPIO Setting (eth1) */
4378385bf2SNobuhiro Iwamatsu 	dat = inw(PSEL1);
4478385bf2SNobuhiro Iwamatsu 	writew(((dat & ~0xff00) | 0x2400), PSEL1);
4578385bf2SNobuhiro Iwamatsu 	writew(0, PFCR);
4678385bf2SNobuhiro Iwamatsu 	writew(0, PGCR);
4778385bf2SNobuhiro Iwamatsu 	writew(0, PHCR);
4878385bf2SNobuhiro Iwamatsu 
4978385bf2SNobuhiro Iwamatsu 	return 0;
5078385bf2SNobuhiro Iwamatsu }
5178385bf2SNobuhiro Iwamatsu 
led_set_state(unsigned short value)5278385bf2SNobuhiro Iwamatsu void led_set_state(unsigned short value)
5378385bf2SNobuhiro Iwamatsu {
5478385bf2SNobuhiro Iwamatsu }
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