xref: /rk3399_rockchip-uboot/board/freescale/mx31ads/mx31ads.c (revision 326ea986ac150acdc7656d57fca647db80b50158)
1f5acb9fdSJean-Christophe PLAGNIOL-VILLARD /*
2f5acb9fdSJean-Christophe PLAGNIOL-VILLARD  * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3f5acb9fdSJean-Christophe PLAGNIOL-VILLARD  *
4*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
5f5acb9fdSJean-Christophe PLAGNIOL-VILLARD  */
6f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
7f5acb9fdSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
8b1c0eaacSBen Warren #include <netdev.h>
9f5acb9fdSJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h>
1086271115SStefano Babic #include <asm/arch/clock.h>
1186271115SStefano Babic #include <asm/arch/imx-regs.h>
1247c5455aSHelmut Raiger #include <asm/arch/sys_proto.h>
13f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
14f5acb9fdSJean-Christophe PLAGNIOL-VILLARD DECLARE_GLOBAL_DATA_PTR;
15f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
dram_init(void)16f5acb9fdSJean-Christophe PLAGNIOL-VILLARD int dram_init(void)
17f5acb9fdSJean-Christophe PLAGNIOL-VILLARD {
184ac2e2d6SFabio Estevam 	/* dram_init must store complete ramsize in gd->ram_size */
19a55d23ccSAlbert ARIBAUD 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
204ac2e2d6SFabio Estevam 				PHYS_SDRAM_1_SIZE);
21f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	return 0;
22f5acb9fdSJean-Christophe PLAGNIOL-VILLARD }
23f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
board_early_init_f(void)244ac2e2d6SFabio Estevam int board_early_init_f(void)
25f5acb9fdSJean-Christophe PLAGNIOL-VILLARD {
26f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	int i;
27f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
28f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* CS0: Nor Flash */
29f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/*
30f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	 * CS0L and CS0A values are from the RedBoot sources by Freescale
31f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	 * and are also equal to those used by Sascha Hauer for the Phytec
32f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	 * i.MX31 board. CS0U is just a slightly optimized hardware default:
33f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	 * the only non-zero field "Wait State Control" is set to half the
34f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	 * default value.
35f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	 */
3647c5455aSHelmut Raiger 	static const struct mxc_weimcs cs0 = {
3747c5455aSHelmut Raiger 		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
3847c5455aSHelmut Raiger 		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  0, 15, 0,  0,  0),
3947c5455aSHelmut Raiger 		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
4047c5455aSHelmut Raiger 		CSCR_L(1,  0,   0,   0,  0,  1,  5,  0,  0,  0,   1,   1),
4147c5455aSHelmut Raiger 		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
4247c5455aSHelmut Raiger 		CSCR_A(0,   0,  7,  2,  0,  0,  2,  1,  0,  0,  0,  0,   0,   0)
4347c5455aSHelmut Raiger 	};
4447c5455aSHelmut Raiger 
4547c5455aSHelmut Raiger 	mxc_setup_weimcs(0, &cs0);
46f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
47f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* setup pins for UART1 */
48f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
49f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
50f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
51f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
52f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
53f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* SPI2 */
54f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
55f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
56f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
57f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
58f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
59f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
60f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
61f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
62f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* start SPI2 clock */
63f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
64f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
65f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* PBC setup */
66f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* Enable UART transceivers also reset the Ethernet/external UART */
67f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	readw(CS4_BASE + 4);
68f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
69f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	writew(0x8023, CS4_BASE + 4);
70f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
71f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* RedBoot also has an empty loop with 100000 iterations here -
72f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	 * clock doesn't run yet */
73f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	for (i = 0; i < 100000; i++)
74f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 		;
75f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
76f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* Clear the reset, toggle the LEDs */
77f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	writew(0xDF, CS4_BASE + 6);
78f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
79f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* clock still doesn't run */
80f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	for (i = 0; i < 100000; i++)
81f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 		;
82f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
83f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	/* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
84f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	readb(CS4_BASE + 8);
85f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	readb(CS4_BASE + 7);
86f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	readb(CS4_BASE + 8);
87f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	readb(CS4_BASE + 7);
88f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
894ac2e2d6SFabio Estevam 	return 0;
904ac2e2d6SFabio Estevam }
914ac2e2d6SFabio Estevam 
board_init(void)924ac2e2d6SFabio Estevam int board_init(void)
934ac2e2d6SFabio Estevam {
94f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	gd->bd->bi_boot_params = 0x80000100;	/* adress of boot parameters */
95f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
96f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	return 0;
97f5acb9fdSJean-Christophe PLAGNIOL-VILLARD }
98f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 
checkboard(void)99f5acb9fdSJean-Christophe PLAGNIOL-VILLARD int checkboard(void)
100f5acb9fdSJean-Christophe PLAGNIOL-VILLARD {
101f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	printf("Board: MX31ADS\n");
102f5acb9fdSJean-Christophe PLAGNIOL-VILLARD 	return 0;
103f5acb9fdSJean-Christophe PLAGNIOL-VILLARD }
104b1c0eaacSBen Warren 
105b1c0eaacSBen Warren #ifdef CONFIG_CMD_NET
board_eth_init(bd_t * bis)106b1c0eaacSBen Warren int board_eth_init(bd_t *bis)
107b1c0eaacSBen Warren {
108b1c0eaacSBen Warren 	int rc = 0;
109b1c0eaacSBen Warren #ifdef CONFIG_CS8900
110b1c0eaacSBen Warren 	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
111b1c0eaacSBen Warren #endif
112b1c0eaacSBen Warren 	return rc;
113b1c0eaacSBen Warren }
114b1c0eaacSBen Warren #endif
115