1*552a848eSStefano Babic /*
2*552a848eSStefano Babic * Copyright 2015 Freescale Semiconductor, Inc.
3*552a848eSStefano Babic *
4*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+
5*552a848eSStefano Babic */
6*552a848eSStefano Babic
7*552a848eSStefano Babic #include <asm/io.h>
8*552a848eSStefano Babic #include <asm/arch/imx-regs.h>
9*552a848eSStefano Babic #include <asm/arch/clock.h>
10*552a848eSStefano Babic #include <asm/arch/sys_proto.h>
11*552a848eSStefano Babic #include <asm/mach-imx/boot_mode.h>
12*552a848eSStefano Babic #include <asm/arch/crm_regs.h>
13*552a848eSStefano Babic
init_aips(void)14*552a848eSStefano Babic void init_aips(void)
15*552a848eSStefano Babic {
16*552a848eSStefano Babic struct aipstz_regs *aips1, *aips2, *aips3;
17*552a848eSStefano Babic
18*552a848eSStefano Babic aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
19*552a848eSStefano Babic aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
20*552a848eSStefano Babic aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
21*552a848eSStefano Babic
22*552a848eSStefano Babic /*
23*552a848eSStefano Babic * Set all MPROTx to be non-bufferable, trusted for R/W,
24*552a848eSStefano Babic * not forced to user-mode.
25*552a848eSStefano Babic */
26*552a848eSStefano Babic writel(0x77777777, &aips1->mprot0);
27*552a848eSStefano Babic writel(0x77777777, &aips1->mprot1);
28*552a848eSStefano Babic writel(0x77777777, &aips2->mprot0);
29*552a848eSStefano Babic writel(0x77777777, &aips2->mprot1);
30*552a848eSStefano Babic
31*552a848eSStefano Babic /*
32*552a848eSStefano Babic * Set all OPACRx to be non-bufferable, not require
33*552a848eSStefano Babic * supervisor privilege level for access,allow for
34*552a848eSStefano Babic * write access and untrusted master access.
35*552a848eSStefano Babic */
36*552a848eSStefano Babic writel(0x00000000, &aips1->opacr0);
37*552a848eSStefano Babic writel(0x00000000, &aips1->opacr1);
38*552a848eSStefano Babic writel(0x00000000, &aips1->opacr2);
39*552a848eSStefano Babic writel(0x00000000, &aips1->opacr3);
40*552a848eSStefano Babic writel(0x00000000, &aips1->opacr4);
41*552a848eSStefano Babic writel(0x00000000, &aips2->opacr0);
42*552a848eSStefano Babic writel(0x00000000, &aips2->opacr1);
43*552a848eSStefano Babic writel(0x00000000, &aips2->opacr2);
44*552a848eSStefano Babic writel(0x00000000, &aips2->opacr3);
45*552a848eSStefano Babic writel(0x00000000, &aips2->opacr4);
46*552a848eSStefano Babic
47*552a848eSStefano Babic if (is_mx6ull() || is_mx6sx() || is_mx7()) {
48*552a848eSStefano Babic /*
49*552a848eSStefano Babic * Set all MPROTx to be non-bufferable, trusted for R/W,
50*552a848eSStefano Babic * not forced to user-mode.
51*552a848eSStefano Babic */
52*552a848eSStefano Babic writel(0x77777777, &aips3->mprot0);
53*552a848eSStefano Babic writel(0x77777777, &aips3->mprot1);
54*552a848eSStefano Babic
55*552a848eSStefano Babic /*
56*552a848eSStefano Babic * Set all OPACRx to be non-bufferable, not require
57*552a848eSStefano Babic * supervisor privilege level for access,allow for
58*552a848eSStefano Babic * write access and untrusted master access.
59*552a848eSStefano Babic */
60*552a848eSStefano Babic writel(0x00000000, &aips3->opacr0);
61*552a848eSStefano Babic writel(0x00000000, &aips3->opacr1);
62*552a848eSStefano Babic writel(0x00000000, &aips3->opacr2);
63*552a848eSStefano Babic writel(0x00000000, &aips3->opacr3);
64*552a848eSStefano Babic writel(0x00000000, &aips3->opacr4);
65*552a848eSStefano Babic }
66*552a848eSStefano Babic }
67*552a848eSStefano Babic
imx_set_wdog_powerdown(bool enable)68*552a848eSStefano Babic void imx_set_wdog_powerdown(bool enable)
69*552a848eSStefano Babic {
70*552a848eSStefano Babic struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
71*552a848eSStefano Babic struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
72*552a848eSStefano Babic struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
73*552a848eSStefano Babic #ifdef CONFIG_MX7D
74*552a848eSStefano Babic struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
75*552a848eSStefano Babic #endif
76*552a848eSStefano Babic
77*552a848eSStefano Babic /* Write to the PDE (Power Down Enable) bit */
78*552a848eSStefano Babic writew(enable, &wdog1->wmcr);
79*552a848eSStefano Babic writew(enable, &wdog2->wmcr);
80*552a848eSStefano Babic
81*552a848eSStefano Babic if (is_mx6sx() || is_mx6ul() || is_mx7())
82*552a848eSStefano Babic writew(enable, &wdog3->wmcr);
83*552a848eSStefano Babic #ifdef CONFIG_MX7D
84*552a848eSStefano Babic writew(enable, &wdog4->wmcr);
85*552a848eSStefano Babic #endif
86*552a848eSStefano Babic }
87*552a848eSStefano Babic
88*552a848eSStefano Babic #define SRC_SCR_WARM_RESET_ENABLE 0
89*552a848eSStefano Babic
init_src(void)90*552a848eSStefano Babic void init_src(void)
91*552a848eSStefano Babic {
92*552a848eSStefano Babic struct src *src_regs = (struct src *)SRC_BASE_ADDR;
93*552a848eSStefano Babic u32 val;
94*552a848eSStefano Babic
95*552a848eSStefano Babic /*
96*552a848eSStefano Babic * force warm reset sources to generate cold reset
97*552a848eSStefano Babic * for a more reliable restart
98*552a848eSStefano Babic */
99*552a848eSStefano Babic val = readl(&src_regs->scr);
100*552a848eSStefano Babic val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
101*552a848eSStefano Babic writel(val, &src_regs->scr);
102*552a848eSStefano Babic }
103*552a848eSStefano Babic
104*552a848eSStefano Babic #ifdef CONFIG_CMD_BMODE
boot_mode_apply(unsigned cfg_val)105*552a848eSStefano Babic void boot_mode_apply(unsigned cfg_val)
106*552a848eSStefano Babic {
107*552a848eSStefano Babic unsigned reg;
108*552a848eSStefano Babic struct src *psrc = (struct src *)SRC_BASE_ADDR;
109*552a848eSStefano Babic writel(cfg_val, &psrc->gpr9);
110*552a848eSStefano Babic reg = readl(&psrc->gpr10);
111*552a848eSStefano Babic if (cfg_val)
112*552a848eSStefano Babic reg |= 1 << 28;
113*552a848eSStefano Babic else
114*552a848eSStefano Babic reg &= ~(1 << 28);
115*552a848eSStefano Babic writel(reg, &psrc->gpr10);
116*552a848eSStefano Babic }
117*552a848eSStefano Babic #endif
118*552a848eSStefano Babic
119*552a848eSStefano Babic #if defined(CONFIG_MX6)
imx6_src_get_boot_mode(void)120*552a848eSStefano Babic u32 imx6_src_get_boot_mode(void)
121*552a848eSStefano Babic {
122*552a848eSStefano Babic if (imx6_is_bmode_from_gpr9())
123*552a848eSStefano Babic return readl(&src_base->gpr9);
124*552a848eSStefano Babic else
125*552a848eSStefano Babic return readl(&src_base->sbmr1);
126*552a848eSStefano Babic }
127*552a848eSStefano Babic #endif
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