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Searched refs:typ (Results 1 – 20 of 20) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/sunxi/
H A Dlcdc.c20 delay = mode->vfront_porch.typ + mode->vsync_len.typ + in lcdc_get_clk_delay()
21 mode->vback_porch.typ; in lcdc_get_clk_delay()
90 writel(SUNXI_LCDC_X(mode->hactive.typ) | in lcdc_tcon0_mode_set()
91 SUNXI_LCDC_Y(mode->vactive.typ), &lcdc->tcon0_timing_active); in lcdc_tcon0_mode_set()
93 bp = mode->hsync_len.typ + mode->hback_porch.typ; in lcdc_tcon0_mode_set()
94 total = mode->hactive.typ + mode->hfront_porch.typ + bp; in lcdc_tcon0_mode_set()
98 bp = mode->vsync_len.typ + mode->vback_porch.typ; in lcdc_tcon0_mode_set()
99 total = mode->vactive.typ + mode->vfront_porch.typ + bp; in lcdc_tcon0_mode_set()
104 writel(SUNXI_LCDC_X(mode->hsync_len.typ) | in lcdc_tcon0_mode_set()
105 SUNXI_LCDC_Y(mode->vsync_len.typ), &lcdc->tcon0_timing_sync); in lcdc_tcon0_mode_set()
[all …]
H A Dsunxi_de2.c78 u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ); in sunxi_de2_mode_set()
169 writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch); in sunxi_de2_mode_set()
217 uc_priv->xsize = timing.hactive.typ; in sunxi_de2_init()
218 uc_priv->ysize = timing.vactive.typ; in sunxi_de2_init()
H A Dsunxi_display.c728 timing->pixelclock.typ = mode->pixclock_khz * 1000; in sunxi_ctfb_mode_to_display_timing()
730 timing->hactive.typ = mode->xres; in sunxi_ctfb_mode_to_display_timing()
731 timing->hfront_porch.typ = mode->right_margin; in sunxi_ctfb_mode_to_display_timing()
732 timing->hback_porch.typ = mode->left_margin; in sunxi_ctfb_mode_to_display_timing()
733 timing->hsync_len.typ = mode->hsync_len; in sunxi_ctfb_mode_to_display_timing()
735 timing->vactive.typ = mode->yres; in sunxi_ctfb_mode_to_display_timing()
736 timing->vfront_porch.typ = mode->lower_margin; in sunxi_ctfb_mode_to_display_timing()
737 timing->vback_porch.typ = mode->upper_margin; in sunxi_ctfb_mode_to_display_timing()
738 timing->vsync_len.typ = mode->vsync_len; in sunxi_ctfb_mode_to_display_timing()
H A Dsunxi_dw_hdmi.c248 int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ); in sunxi_dw_hdmi_lcdc_init()
/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Ddisplay.c31 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
33 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
34 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
35 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
36 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
51 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
52 refresh % 1000, timing->pixelclock.typ); in print_mode()
66 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, in update_display_mode()
69 writel(((timing->vback_porch.typ - vref_to_sync) << 16) | in update_display_mode()
70 timing->hback_porch.typ, &disp_ctrl->disp.back_porch); in update_display_mode()
[all …]
H A Dsor.c639 vtotal = timing->vsync_len.typ + timing->vback_porch.typ + in tegra_dc_sor_config_panel()
640 timing->vactive.typ + timing->vfront_porch.typ; in tegra_dc_sor_config_panel()
641 htotal = timing->hsync_len.typ + timing->hback_porch.typ + in tegra_dc_sor_config_panel()
642 timing->hactive.typ + timing->hfront_porch.typ; in tegra_dc_sor_config_panel()
648 vsync_end = timing->vsync_len.typ - 1; in tegra_dc_sor_config_panel()
649 hsync_end = timing->hsync_len.typ - 1; in tegra_dc_sor_config_panel()
654 vblank_end = vsync_end + timing->vback_porch.typ; in tegra_dc_sor_config_panel()
655 hblank_end = hsync_end + timing->hback_porch.typ; in tegra_dc_sor_config_panel()
660 vblank_start = vblank_end + timing->vactive.typ; in tegra_dc_sor_config_panel()
661 hblank_start = hblank_end + timing->hactive.typ; in tegra_dc_sor_config_panel()
H A Ddp.c510 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
514 if ((u64)timing->pixelclock.typ * link_cfg->bits_per_pixel >= in tegra_dc_dp_calc_config()
518 num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ, in tegra_dc_dp_calc_config()
519 timing->pixelclock.typ)); in tegra_dc_dp_calc_config()
521 ratio_f = (u64)timing->pixelclock.typ * link_cfg->bits_per_pixel * f; in tegra_dc_dp_calc_config()
601 num_symbols_per_line = (timing->hactive.typ * in tegra_dc_dp_calc_config()
622 link_cfg->hblank_sym = (int)lldiv(((uint64_t)timing->hback_porch.typ + in tegra_dc_dp_calc_config()
623 timing->hfront_porch.typ + timing->hsync_len.typ - 7) * in tegra_dc_dp_calc_config()
624 link_rate, timing->pixelclock.typ) - in tegra_dc_dp_calc_config()
639 link_cfg->vblank_sym = (int)lldiv(((uint64_t)timing->hactive.typ - 25) in tegra_dc_dp_calc_config()
[all …]
/rk3399_rockchip-uboot/drivers/video/
H A Datmel_lcdfb.c135 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
141 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
142 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
165 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET; in atmel_fb_init()
166 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET; in atmel_fb_init()
167 value |= timing->vfront_porch.typ; in atmel_fb_init()
173 value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET; in atmel_fb_init()
174 value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET; in atmel_fb_init()
175 value |= (timing->hback_porch.typ - 1); in atmel_fb_init()
179 value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET; in atmel_fb_init()
[all …]
H A Ddw_hdmi.c397 hbl = edid->hback_porch.typ + edid->hfront_porch.typ + in hdmi_av_composer()
398 edid->hsync_len.typ; in hdmi_av_composer()
399 vbl = edid->vback_porch.typ + edid->vfront_porch.typ + in hdmi_av_composer()
400 edid->vsync_len.typ; in hdmi_av_composer()
428 hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1); in hdmi_av_composer()
429 hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0); in hdmi_av_composer()
432 hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1); in hdmi_av_composer()
433 hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0); in hdmi_av_composer()
443 hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1); in hdmi_av_composer()
444 hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0); in hdmi_av_composer()
[all …]
H A Datmel_hlcdfb.c326 value = priv->clk_rate / timing->pixelclock.typ; in atmel_hlcdc_init()
327 if (priv->clk_rate % timing->pixelclock.typ) in atmel_hlcdc_init()
386 value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1); in atmel_hlcdc_init()
387 value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1); in atmel_hlcdc_init()
390 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ); in atmel_hlcdc_init()
391 value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1); in atmel_hlcdc_init()
394 value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1); in atmel_hlcdc_init()
395 value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1); in atmel_hlcdc_init()
399 value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1); in atmel_hlcdc_init()
400 value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1); in atmel_hlcdc_init()
[all …]
H A Dtegra.c111 writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width); in update_display_mode()
112 writel(dt->hback_porch.typ | dt->vback_porch.typ << 16, in update_display_mode()
114 writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16, in update_display_mode()
116 writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); in update_display_mode()
366 priv->width = timing->hactive.typ; in tegra_lcd_ofdata_to_platdata()
367 priv->height = timing->vactive.typ; in tegra_lcd_ofdata_to_platdata()
368 priv->pixel_clock = timing->pixelclock.typ; in tegra_lcd_ofdata_to_platdata()
/rk3399_rockchip-uboot/drivers/video/rockchip/
H A Drk_vop.c42 u32 hactive = edid->hactive.typ; in rkvop_enable()
43 u32 vactive = edid->vactive.typ; in rkvop_enable()
48 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) | in rkvop_enable()
49 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ), in rkvop_enable()
146 u32 hactive = edid->hactive.typ; in rkvop_mode_set()
147 u32 vactive = edid->vactive.typ; in rkvop_mode_set()
148 u32 hsync_len = edid->hsync_len.typ; in rkvop_mode_set()
149 u32 hback_porch = edid->hback_porch.typ; in rkvop_mode_set()
150 u32 vsync_len = edid->vsync_len.typ; in rkvop_mode_set()
151 u32 vback_porch = edid->vback_porch.typ; in rkvop_mode_set()
[all …]
H A Drk_mipi.c92 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
93 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); in rk_mipi_dsi_enable()
94 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ in rk_mipi_dsi_enable()
95 + timing->hback_porch.typ + timing->hactive.typ in rk_mipi_dsi_enable()
96 + timing->hfront_porch.typ)); in rk_mipi_dsi_enable()
97 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); in rk_mipi_dsi_enable()
98 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); in rk_mipi_dsi_enable()
99 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ); in rk_mipi_dsi_enable()
100 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ); in rk_mipi_dsi_enable()
H A Drk3399_mipi.c88 priv->pix_clk = timing->pixelclock.typ; in rk_display_enable()
H A Drk3288_mipi.c96 priv->pix_clk = timing->pixelclock.typ; in rk_mipi_enable()
/rk3399_rockchip-uboot/drivers/video/bridge/
H A Danx6345.c365 timing.hactive.typ, timing.vactive.typ, bpp); in anx6345_enable()
/rk3399_rockchip-uboot/drivers/core/
H A Dofnode.c431 result->typ = ofnode_read_u32_default(node, name, 0); in decode_timing_property()
432 result->min = result->typ; in decode_timing_property()
433 result->max = result->typ; in decode_timing_property()
/rk3399_rockchip-uboot/include/
H A Dfdtdec.h902 u32 typ; member
/rk3399_rockchip-uboot/lib/
H A Dfdtdec.c1074 result->typ = fdtdec_get_int(blob, node, name, 0); in decode_timing_property()
1075 result->min = result->typ; in decode_timing_property()
1076 result->max = result->typ; in decode_timing_property()
/rk3399_rockchip-uboot/common/
H A Dedid.c1759 entry->typ = value; in set_entry()
1817 timing->pixelclock.typ, in decode_timing()