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Searched refs:tshsl (Results 1 – 11 of 11) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsocfpga_cyclone5_vining_fpga.dts83 tshsl-ns = <50>;
100 tshsl-ns = <50>;
H A Dstv0991.dts47 tshsl-ns = <50>;
H A Dsocfpga_cyclone5_sockit.dts88 tshsl-ns = <50>;
H A Dsocfpga_cyclone5_socrates.dts78 tshsl-ns = <50>;
H A Dsocfpga_cyclone5_sr1500.dts96 tshsl-ns = <50>;
H A Dsocfpga_arria5_socdk.dts98 tshsl-ns = <50>;
H A Dsocfpga_cyclone5_is1.dts97 tshsl-ns = <50>;
H A Dsocfpga_cyclone5_socdk.dts108 tshsl-ns = <50>;
H A Dkeystone-k2g-evm.dts79 tshsl-ns = <392>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/spi/
H A Dspi-cadence.txt18 - tshsl-ns : Added delay in master reference clocks (ref_clk) for
/rk3399_rockchip-uboot/drivers/spi/
H A Dcadence_qspi_apb.c342 unsigned int tshsl, tchsh, tslch, tsd2d; in cadence_qspi_apb_delay() local
358 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns); in cadence_qspi_apb_delay()
363 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) in cadence_qspi_apb_delay()