1ae9996c8SStefan Roese/* 2ae9996c8SStefan Roese * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3ae9996c8SStefan Roese * 4ae9996c8SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5ae9996c8SStefan Roese */ 6ae9996c8SStefan Roese 7ae9996c8SStefan Roese#include "socfpga_cyclone5.dtsi" 8ae9996c8SStefan Roese 9ae9996c8SStefan Roese/ { 10ae9996c8SStefan Roese model = "SoCFPGA Cyclone V SR1500"; 11ae9996c8SStefan Roese compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga"; 12ae9996c8SStefan Roese 13ae9996c8SStefan Roese chosen { 14ae9996c8SStefan Roese bootargs = "console=ttyS0,115200"; 15ae9996c8SStefan Roese }; 16ae9996c8SStefan Roese 17ae9996c8SStefan Roese aliases { 18ae9996c8SStefan Roese /* 19*84f841c5SStefan Roese * This allows the ethaddr uboot environment variable 20ae9996c8SStefan Roese * contents to be added to the gmac1 device tree blob. 21ae9996c8SStefan Roese */ 22ae9996c8SStefan Roese ethernet0 = &gmac1; 23ae9996c8SStefan Roese }; 24ae9996c8SStefan Roese 25ae9996c8SStefan Roese memory@0 { 26ae9996c8SStefan Roese name = "memory"; 27ae9996c8SStefan Roese device_type = "memory"; 28ae9996c8SStefan Roese reg = <0x0 0x40000000>; /* 1GB */ 29ae9996c8SStefan Roese }; 30ae9996c8SStefan Roese 31ae9996c8SStefan Roese soc { 32ae9996c8SStefan Roese u-boot,dm-pre-reloc; 33ae9996c8SStefan Roese }; 34ae9996c8SStefan Roese}; 35ae9996c8SStefan Roese 36ae9996c8SStefan Roese&gmac1 { 37ae9996c8SStefan Roese status = "okay"; 38ae9996c8SStefan Roese phy-mode = "rgmii"; 39ae9996c8SStefan Roese}; 40ae9996c8SStefan Roese 41ae9996c8SStefan Roese&gpio0 { 42ae9996c8SStefan Roese status = "okay"; 43ae9996c8SStefan Roese}; 44ae9996c8SStefan Roese 45ae9996c8SStefan Roese&gpio1 { 46ae9996c8SStefan Roese status = "okay"; 47ae9996c8SStefan Roese}; 48ae9996c8SStefan Roese 49ae9996c8SStefan Roese&gpio2 { 50ae9996c8SStefan Roese status = "okay"; 51ae9996c8SStefan Roese}; 52ae9996c8SStefan Roese 53ae9996c8SStefan Roese&i2c0 { 54ae9996c8SStefan Roese status = "okay"; 55ae9996c8SStefan Roese speed-mode = <0>; 56ae9996c8SStefan Roese}; 57ae9996c8SStefan Roese 58ae9996c8SStefan Roese&i2c1 { 59ae9996c8SStefan Roese status = "okay"; 60ae9996c8SStefan Roese speed-mode = <0>; 61ae9996c8SStefan Roese}; 62ae9996c8SStefan Roese 63ae9996c8SStefan Roese&mmc0 { 64ae9996c8SStefan Roese status = "okay"; 65ae9996c8SStefan Roese bus-width = <8>; 66ae9996c8SStefan Roese u-boot,dm-pre-reloc; 67ae9996c8SStefan Roese}; 68ae9996c8SStefan Roese 69ae9996c8SStefan Roese&uart0 { 70ae9996c8SStefan Roese status = "okay"; 71ae9996c8SStefan Roese}; 72ae9996c8SStefan Roese 73ae9996c8SStefan Roese&usb1 { 74ae9996c8SStefan Roese status = "okay"; 75ae9996c8SStefan Roese}; 76ae9996c8SStefan Roese 77ae9996c8SStefan Roese&watchdog0 { 78ae9996c8SStefan Roese status = "okay"; 79ae9996c8SStefan Roese}; 80ae9996c8SStefan Roese 81ae9996c8SStefan Roese&qspi { 82ae9996c8SStefan Roese status = "okay"; 83ae9996c8SStefan Roese u-boot,dm-pre-reloc; 84ae9996c8SStefan Roese 85ae9996c8SStefan Roese flash0: n25q00@0 { 86ae9996c8SStefan Roese u-boot,dm-pre-reloc; 87ae9996c8SStefan Roese #address-cells = <1>; 88ae9996c8SStefan Roese #size-cells = <1>; 89ae9996c8SStefan Roese compatible = "n25q00", "spi-flash"; 90ae9996c8SStefan Roese reg = <0>; /* chip select */ 9193d9fc26SStefan Roese spi-max-frequency = <100000000>; 92ae9996c8SStefan Roese m25p,fast-read; 93ae9996c8SStefan Roese page-size = <256>; 94ae9996c8SStefan Roese block-size = <16>; /* 2^16, 64KB */ 95ae9996c8SStefan Roese read-delay = <4>; /* delay value in read data capture register */ 96ae9996c8SStefan Roese tshsl-ns = <50>; 97ae9996c8SStefan Roese tsd2d-ns = <50>; 98ae9996c8SStefan Roese tchsh-ns = <4>; 99ae9996c8SStefan Roese tslch-ns = <4>; 100ae9996c8SStefan Roese }; 101ae9996c8SStefan Roese}; 102