| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr3_1333.c | 33 u8 tcl = 6; /* CL 12 */ in mctl_set_timing_params() local
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
62 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 33 u8 tcl = 6; /* CL 12 */ in mctl_set_timing_params() local
45 u8 trd2wr = tcl + 4 + 5 - tcwl + 1; in mctl_set_timing_params()
58 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| H A D | ddr2_v3s.c | 33 u8 tcl = 3; /* CL 6 */ in mctl_set_timing_params() local
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
59 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
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| /rk3399_rockchip-uboot/board/tcl/sl50/ |
| H A D | MAINTAINERS | 4 F: board/tcl/sl50/
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| H A D | Kconfig | 7 default "tcl"
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | dmc-rk3368.c | 158 u32 tcl, u32 tal, u32 tcwl) in ddrphy_config() argument
166 clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal); in ddrphy_config()
241 DDR3_MR0_CL(params->pctl_timing.tcl) | in memory_init()
475 pctl_timing->tcl = 6; in pctl_calc_timings()
478 pctl_timing->tcl = 8; in pctl_calc_timings()
481 pctl_timing->tcl = 10; in pctl_calc_timings()
484 pctl_timing->tcl = 11; in pctl_calc_timings()
496 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; in pctl_calc_timings()
562 writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
833 params->pctl_timing.tcl, in setup_sdram()
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| H A D | sdram_rv1108_pctl_phy.c | 331 reg = readl(&priv->pctl->tcl); in pctl_cfg()
359 reg = readl(&priv->pctl->tcl); in pctl_cfg()
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| H A D | sdram_rk3288.c | 253 writel(sdram_params->pctl_timing.tcl - 1, in pctl_cfg()
270 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
273 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
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| H A D | sdram_rk322x.c | 429 writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
443 writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.malta | 12 source /path/to/u-boot/board/imgtec/malta/flash-malta-boot.tcl
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 117 u8 tcl = 6; /* CL 12 */ in auto_set_timing_para() local
129 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
168 trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
175 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
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| H A D | dram_sun8i_a33.c | 117 u8 tcl = 6; /* CL 12 */ in auto_set_timing_para() local
129 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
143 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3288.h | 49 u32 tcl; member
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| H A D | sdram_rk3036.h | 52 u32 tcl; member
249 u32 tcl; member
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| H A D | sdram_rk322x.h | 81 u32 tcl; member
207 u32 tcl; member
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| H A D | sdram_rv1108_pctl_phy.h | 53 u32 tcl; member
269 u32 tcl; member
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| H A D | ddr_rk3368.h | 56 u32 tcl; member
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| H A D | ddr_rk3288.h | 51 u32 tcl; member
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 976 u8 twl, txp, tfaw, tcl; in mx6_lpddr2_cfg() local
1043 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3; in mx6_lpddr2_cfg()
1064 debug("tcl=%d\n", tcl); in mx6_lpddr2_cfg()
1118 (tfaw << 4) | tcl; in mx6_lpddr2_cfg()
1206 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; in mx6_ddr3_cfg() local
1313 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3; in mx6_ddr3_cfg()
1337 debug("tcl=%d\n", tcl); in mx6_ddr3_cfg()
1410 (txpdll << 9) | (tfaw << 4) | tcl; in mx6_ddr3_cfg()
1465 val = ((tcl - 1) << 4) | /* CAS */ in mx6_ddr3_cfg()
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/misc/ |
| H A D | intel,baytrail-fsp.txt | 81 - fsp,dimm-tcl
144 fsp,dimm-tcl = <0xb>;
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| /rk3399_rockchip-uboot/arch/x86/cpu/quark/ |
| H A D | smc.c | 71 uint8_t tcl, wl; in prog_ddr_timing_control() local
89 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
90 trp = tcl; /* Per CAT MRC */ in prog_ddr_timing_control()
91 trcd = tcl; /* Per CAT MRC */ in prog_ddr_timing_control()
107 tmp1 = tcl - 5; in prog_ddr_timing_control()
108 dtr0 |= ((tcl - 5) << 12); in prog_ddr_timing_control()
147 dtr3 |= ((tcl - 5 + 1) << 8); in prog_ddr_timing_control()
150 dtr3 |= ((tcl - 5 + 1) << 8); in prog_ddr_timing_control()
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| /rk3399_rockchip-uboot/board/freescale/mx6qarm2/ |
| H A D | imximage_mx6dl.cfg | 285 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
297 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun6i.h | 79 u32 tcl; /* 0xe8 */ member
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 64 tcl
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/ |
| H A D | sdram_rk3066.c | 228 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
231 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
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