1*451da917SYouMin Chen /* 2*451da917SYouMin Chen * Copyright (c) 2015 Google, Inc 3*451da917SYouMin Chen * 4*451da917SYouMin Chen * Copyright 2014 Rockchip Inc. 5*451da917SYouMin Chen * 6*451da917SYouMin Chen * SPDX-License-Identifier: GPL-2.0 7*451da917SYouMin Chen */ 8*451da917SYouMin Chen 9*451da917SYouMin Chen #ifndef _ASM_ARCH_RK3288_SDRAM_H__ 10*451da917SYouMin Chen #define _ASM_ARCH_RK3288_SDRAM_H__ 11*451da917SYouMin Chen 12*451da917SYouMin Chen struct rk3288_sdram_channel { 13*451da917SYouMin Chen /* 14*451da917SYouMin Chen * bit width in address, eg: 15*451da917SYouMin Chen * 8 banks using 3 bit to address, 16*451da917SYouMin Chen * 2 cs using 1 bit to address. 17*451da917SYouMin Chen */ 18*451da917SYouMin Chen u8 rank; 19*451da917SYouMin Chen u8 col; 20*451da917SYouMin Chen u8 bk; 21*451da917SYouMin Chen u8 bw; 22*451da917SYouMin Chen u8 dbw; 23*451da917SYouMin Chen u8 row_3_4; 24*451da917SYouMin Chen u8 cs0_row; 25*451da917SYouMin Chen u8 cs1_row; 26*451da917SYouMin Chen #if CONFIG_IS_ENABLED(OF_PLATDATA) 27*451da917SYouMin Chen /* 28*451da917SYouMin Chen * For of-platdata, which would otherwise convert this into two 29*451da917SYouMin Chen * byte-swapped integers. With a size of 9 bytes, this struct will 30*451da917SYouMin Chen * appear in of-platdata as a byte array. 31*451da917SYouMin Chen * 32*451da917SYouMin Chen * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) 33*451da917SYouMin Chen */ 34*451da917SYouMin Chen u8 dummy; 35*451da917SYouMin Chen #endif 36*451da917SYouMin Chen }; 37*451da917SYouMin Chen 38*451da917SYouMin Chen struct rk3288_sdram_pctl_timing { 39*451da917SYouMin Chen u32 togcnt1u; 40*451da917SYouMin Chen u32 tinit; 41*451da917SYouMin Chen u32 trsth; 42*451da917SYouMin Chen u32 togcnt100n; 43*451da917SYouMin Chen u32 trefi; 44*451da917SYouMin Chen u32 tmrd; 45*451da917SYouMin Chen u32 trfc; 46*451da917SYouMin Chen u32 trp; 47*451da917SYouMin Chen u32 trtw; 48*451da917SYouMin Chen u32 tal; 49*451da917SYouMin Chen u32 tcl; 50*451da917SYouMin Chen u32 tcwl; 51*451da917SYouMin Chen u32 tras; 52*451da917SYouMin Chen u32 trc; 53*451da917SYouMin Chen u32 trcd; 54*451da917SYouMin Chen u32 trrd; 55*451da917SYouMin Chen u32 trtp; 56*451da917SYouMin Chen u32 twr; 57*451da917SYouMin Chen u32 twtr; 58*451da917SYouMin Chen u32 texsr; 59*451da917SYouMin Chen u32 txp; 60*451da917SYouMin Chen u32 txpdll; 61*451da917SYouMin Chen u32 tzqcs; 62*451da917SYouMin Chen u32 tzqcsi; 63*451da917SYouMin Chen u32 tdqs; 64*451da917SYouMin Chen u32 tcksre; 65*451da917SYouMin Chen u32 tcksrx; 66*451da917SYouMin Chen u32 tcke; 67*451da917SYouMin Chen u32 tmod; 68*451da917SYouMin Chen u32 trstl; 69*451da917SYouMin Chen u32 tzqcl; 70*451da917SYouMin Chen u32 tmrr; 71*451da917SYouMin Chen u32 tckesr; 72*451da917SYouMin Chen u32 tdpd; 73*451da917SYouMin Chen }; 74*451da917SYouMin Chen check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); 75*451da917SYouMin Chen 76*451da917SYouMin Chen struct rk3288_sdram_phy_timing { 77*451da917SYouMin Chen u32 dtpr0; 78*451da917SYouMin Chen u32 dtpr1; 79*451da917SYouMin Chen u32 dtpr2; 80*451da917SYouMin Chen u32 mr[4]; 81*451da917SYouMin Chen }; 82*451da917SYouMin Chen 83*451da917SYouMin Chen struct rk3288_base_params { 84*451da917SYouMin Chen u32 noc_timing; 85*451da917SYouMin Chen u32 noc_activate; 86*451da917SYouMin Chen u32 ddrconfig; 87*451da917SYouMin Chen u32 ddr_freq; 88*451da917SYouMin Chen u32 dramtype; 89*451da917SYouMin Chen /* 90*451da917SYouMin Chen * DDR Stride is address mapping for DRAM space 91*451da917SYouMin Chen * Stride Ch 0 range Ch1 range Total 92*451da917SYouMin Chen * 0x00 0-256MB 256MB-512MB 512MB 93*451da917SYouMin Chen * 0x05 0-1GB 0-1GB 1GB 94*451da917SYouMin Chen * 0x09 0-2GB 0-2GB 2GB 95*451da917SYouMin Chen * 0x0d 0-4GB 0-4GB 4GB 96*451da917SYouMin Chen * 0x17 N/A 0-4GB 4GB 97*451da917SYouMin Chen * 0x1a 0-4GB 4GB-8GB 8GB 98*451da917SYouMin Chen */ 99*451da917SYouMin Chen u32 stride; 100*451da917SYouMin Chen u32 odt; 101*451da917SYouMin Chen }; 102*451da917SYouMin Chen 103*451da917SYouMin Chen #endif 104