Home
last modified time | relevance | path

Searched refs:t0 (Results 1 – 17 of 17) sorted by relevance

/rk3399_rockchip-uboot/board/pb1x00/
H A Dlowlevel_init.S27 li t0, MEM_STCFG1
29 sw t1, 0(t0)
31 li t0, MEM_STTIME1
33 sw t1, 0(t0)
35 li t0, MEM_STADDR1
37 sw t1, 0(t0)
55 li t0, AU1500_SYS_ADDR
57 sw t1, sys_endian(t0)
112 li t0, SYS_CPUPLL
114 sw t1, 0(t0)
[all …]
/rk3399_rockchip-uboot/board/dbau1x00/
H A Dlowlevel_init.S27 li t0, MEM_STCFG2
29 sw t1, 0(t0)
31 li t0, MEM_STTIME2
33 sw t1, 0(t0)
35 li t0, MEM_STADDR2
37 sw t1, 0(t0)
39 li t0, MEM_STCFG1
41 sw t1, 0(t0)
43 li t0, MEM_STTIME1
45 sw t1, 0(t0)
[all …]
/rk3399_rockchip-uboot/board/imgtec/malta/
H A Dlowlevel_init.S32 PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
33 lw t0, 0(t0)
34 srl t0, t0, MALTA_REVISION_CORID_SHF
35 andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
40 beq t0, t1, _gt64120
44 beq t0, t1, _msc01
67 li t0, CPU_TO_GT32(0xdf000000)
68 sw t0, GT_ISD_OFS(t1)
74 li t0, CPU_TO_GT32(0xc0000000)
75 sw t0, GT_PCI0IOLD_OFS(t1)
[all …]
/rk3399_rockchip-uboot/arch/mips/lib/
H A Dcache_init.S126 mfc0 t0, CP0_CONFIG, 1
127 bgez t0, l2_probe_done
137 mfc0 t0, CP0_CONFIG, 2
138 bgez t0, l2_probe_cop0
139 mfc0 t0, CP0_CONFIG, 3
140 bgez t0, l2_probe_cop0
141 mfc0 t0, CP0_CONFIG, 4
142 bgez t0, l2_probe_cop0
145 mfc0 t0, CP0_CONFIG, 5
146 and R_L2_L2C, t0, MIPS_CONF5_L2C
[all …]
/rk3399_rockchip-uboot/arch/mips/cpu/
H A Dcm_init.S17 mfc0 t0, CP0_CONFIG, 1
18 bgez t0, 2f
19 mfc0 t0, CP0_CONFIG, 2
20 bgez t0, 2f
23 mfc0 t0, CP0_CONFIG, 3
24 and t0, t0, MIPS_CONF3_CMGCR
25 beqz t0, 2f
28 1: MFC0 t0, CP0_CMGCRBASE
29 PTR_SLL t0, t0, 4
33 beq t0, t1, 2f
[all …]
H A Dstart.S42 mfc0 t0, CP0_WATCHHI,\sel
43 bgez t0, wr_done
56 li t0, -16
58 and sp, t1, t0 # force 16 byte alignment
61 and sp, sp, t0 # force 16 byte alignment
67 and sp, sp, t0 # force 16 byte alignment
72 move t0, k0
74 PTR_S zero, 0(t0)
75 blt t0, t1, 1b
76 PTR_ADDIU t0, PTRSIZE
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S82 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
83 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
85 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
87 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
90 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
101 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
107 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
111 li t0, CKSEG1ADDR(AR933X_RTC_BASE)
113 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
119 sw t1, AR933X_RTC_REG_RESET(t0)
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S102 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
103 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
106 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
108 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
111 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
115 li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
117 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
123 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
128 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
130 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dsha256_ce_core.S22 t0 .req v22
36 sha256h dg0q, dg1q, t0.4s
37 sha256h2 dg1q, dg2q, t0.4s
40 add t0.4s, v\s0\().4s, \rc\().4s
100 1: add t0.4s, v16.4s, v0.4s
H A Dsha1_ce_core.S22 t0 .req v4
42 sha1\op dg0q, \dg1, t0.4s
44 sha1\op dg0q, dg1s, t0.4s
48 add t0.4s, v\s0\().4s, \rc\().4s
92 1: add t0.4s, v8.4s, k0.4s
/rk3399_rockchip-uboot/board/imgtec/boston/
H A Dlowlevel_init.S29 PTR_LI t0, BOSTON_PLAT_DDR3STAT
30 1: lw t1, 0(t0)
/rk3399_rockchip-uboot/arch/mips/include/asm/
H A Dregdef.h28 #define t0 $8 /* caller saved */ macro
79 #define t0 $12 /* caller saved */ macro
/rk3399_rockchip-uboot/tools/buildman/
H A Dkconfiglib.py664 t0 = tokens.get_next()
665 if t0 is None:
671 if t0 == T_CONFIG or t0 == T_MENUCONFIG:
690 elif t0 == T_SOURCE:
706 elif t0 == end_marker:
710 elif t0 == T_IF:
723 elif t0 == T_COMMENT:
738 elif t0 == T_MENU:
758 elif t0 == T_CHOICE:
801 elif t0 == T_MAINMENU:
[all …]
/rk3399_rockchip-uboot/arch/nds32/cpu/n1213/
H A Dstart.S343 mfsr $t0, CR_ICAC_MEM
346 andi $p0, $t0, ICAC_MEM_KBF_ISZ
359 andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
361 andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
378 mfsr $t0, CR_DCAC_MEM
381 andi $p0, $t0, DCAC_MEM_KBF_DSZ
394 andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
396 andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dspl_pcie_ep_boot.c437 u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0; in pcie_cru_init() local
499 if (phy0_mplla != t0 || phy1_mplla != t1) { in pcie_cru_init()
502 t0 = phy0_mplla; in pcie_cru_init()
584 u32 phy0_status0, phy0_status1, t0 = 0, t1 = 0; in pcie_cru_init() local
644 if (phy0_status0 != t0 || phy0_status1 != t1) { in pcie_cru_init()
647 t0 = phy0_status0; in pcie_cru_init()
/rk3399_rockchip-uboot/include/optee_include/
H A Dtee_api_defines.h419 #define TEE_PARAM_TYPES(t0, t1, t2, t3) \ argument
420 ((t0) | ((t1) << 4) | ((t2) << 8) | ((t3) << 12))
/rk3399_rockchip-uboot/drivers/video/
H A Dstb_truetype.h269 glTexCoord2f(q.s1,q.t0); glVertex2f(q.x1,q.y1);
270 glTexCoord2f(q.s0,q.t0); glVertex2f(q.x0,q.y1);
480 float x0,y0,s0,t0; // top-left member
2574 q->t0 = b->y0 * iph; in stbtt_GetBakedQuad()
3030 q->t0 = b->y0 * iph; in stbtt_GetPackedQuad()