Lines Matching refs:t0
102 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
103 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
106 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
108 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
111 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
115 li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
117 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
123 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
128 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
130 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
131 sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
132 sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
133 sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
135 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
136 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
138 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
142 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
146 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
150 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
153 lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
156 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
159 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
162 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
165 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
168 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
172 sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
176 sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
179 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
181 sw t1, 0xb4(t0)