1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * sha1_ce_core.S - SHA-1 secure hash using ARMv8 Crypto Extensions 4 * 5 * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org> 6 * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org> 7 */ 8 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/system.h> 12#include <asm/macro.h> 13 14 .text 15 .arch armv8-a+crypto 16 17 k0 .req v0 18 k1 .req v1 19 k2 .req v2 20 k3 .req v3 21 22 t0 .req v4 23 t1 .req v5 24 25 dga .req q6 26 dgav .req v6 27 dgb .req s7 28 dgbv .req v7 29 30 dg0q .req q12 31 dg0s .req s12 32 dg0v .req v12 33 dg1s .req s13 34 dg1v .req v13 35 dg2s .req s14 36 37 .macro add_only, op, ev, rc, s0, dg1 38 .ifc \ev, ev 39 add t1.4s, v\s0\().4s, \rc\().4s 40 sha1h dg2s, dg0s 41 .ifnb \dg1 42 sha1\op dg0q, \dg1, t0.4s 43 .else 44 sha1\op dg0q, dg1s, t0.4s 45 .endif 46 .else 47 .ifnb \s0 48 add t0.4s, v\s0\().4s, \rc\().4s 49 .endif 50 sha1h dg1s, dg0s 51 sha1\op dg0q, dg2s, t1.4s 52 .endif 53 .endm 54 55 .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 56 sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s 57 add_only \op, \ev, \rc, \s1, \dg1 58 sha1su1 v\s0\().4s, v\s3\().4s 59 .endm 60 61 .macro loadrc, k, val, tmp 62 movz \tmp, :abs_g0_nc:\val 63 movk \tmp, :abs_g1:\val 64 dup \k, \tmp 65 .endm 66 67 /* 68 * void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src, 69 * uint32_t blocks) 70 */ 71ENTRY(sha1_armv8_ce_process) 72 /* load round constants */ 73 loadrc k0.4s, 0x5a827999, w6 74 loadrc k1.4s, 0x6ed9eba1, w6 75 loadrc k2.4s, 0x8f1bbcdc, w6 76 loadrc k3.4s, 0xca62c1d6, w6 77 78 /* load state (4+1 digest states) */ 79 ld1 {dgav.4s}, [x0] 80 ldr dgb, [x0, #16] 81 82 /* load input (64 bytes into v8->v11 16B vectors) */ 830: ld1 {v8.4s-v11.4s}, [x1], #64 84 sub w2, w2, #1 85#if __BYTE_ORDER == __LITTLE_ENDIAN 86 rev32 v8.16b, v8.16b 87 rev32 v9.16b, v9.16b 88 rev32 v10.16b, v10.16b 89 rev32 v11.16b, v11.16b 90#endif 91 921: add t0.4s, v8.4s, k0.4s 93 mov dg0v.16b, dgav.16b 94 95 add_update c, ev, k0, 8, 9, 10, 11, dgb 96 add_update c, od, k0, 9, 10, 11, 8 97 add_update c, ev, k0, 10, 11, 8, 9 98 add_update c, od, k0, 11, 8, 9, 10 99 add_update c, ev, k1, 8, 9, 10, 11 100 101 add_update p, od, k1, 9, 10, 11, 8 102 add_update p, ev, k1, 10, 11, 8, 9 103 add_update p, od, k1, 11, 8, 9, 10 104 add_update p, ev, k1, 8, 9, 10, 11 105 add_update p, od, k2, 9, 10, 11, 8 106 107 add_update m, ev, k2, 10, 11, 8, 9 108 add_update m, od, k2, 11, 8, 9, 10 109 add_update m, ev, k2, 8, 9, 10, 11 110 add_update m, od, k2, 9, 10, 11, 8 111 add_update m, ev, k3, 10, 11, 8, 9 112 113 add_update p, od, k3, 11, 8, 9, 10 114 add_only p, ev, k3, 9 115 add_only p, od, k3, 10 116 add_only p, ev, k3, 11 117 add_only p, od 118 119 /* update state */ 120 add dgbv.2s, dgbv.2s, dg1v.2s 121 add dgav.4s, dgav.4s, dg0v.4s 122 123 /* loop on next block? */ 124 cbz w2, 2f 125 b 0b 126 127 /* store new state */ 1282: st1 {dgav.4s}, [x0] 129 str dgb, [x0, #16] 130 mov w0, w2 131 ret 132ENDPROC(sha1_armv8_ce_process) 133