1*b2b135d9SPaul Burton/* 2*b2b135d9SPaul Burton * MIPS Coherence Manager (CM) Initialisation 3*b2b135d9SPaul Burton * 4*b2b135d9SPaul Burton * Copyright (c) 2016 Imagination Technologies Ltd. 5*b2b135d9SPaul Burton * 6*b2b135d9SPaul Burton * SPDX-License-Identifier: GPL-2.0+ 7*b2b135d9SPaul Burton */ 8*b2b135d9SPaul Burton 9*b2b135d9SPaul Burton#include <asm/addrspace.h> 10*b2b135d9SPaul Burton#include <asm/asm.h> 11*b2b135d9SPaul Burton#include <asm/cm.h> 12*b2b135d9SPaul Burton#include <asm/mipsregs.h> 13*b2b135d9SPaul Burton#include <asm/regdef.h> 14*b2b135d9SPaul Burton 15*b2b135d9SPaul BurtonLEAF(mips_cm_map) 16*b2b135d9SPaul Burton /* Config3 must exist for a CM to be present */ 17*b2b135d9SPaul Burton mfc0 t0, CP0_CONFIG, 1 18*b2b135d9SPaul Burton bgez t0, 2f 19*b2b135d9SPaul Burton mfc0 t0, CP0_CONFIG, 2 20*b2b135d9SPaul Burton bgez t0, 2f 21*b2b135d9SPaul Burton 22*b2b135d9SPaul Burton /* Check Config3.CMGCR to determine CM presence */ 23*b2b135d9SPaul Burton mfc0 t0, CP0_CONFIG, 3 24*b2b135d9SPaul Burton and t0, t0, MIPS_CONF3_CMGCR 25*b2b135d9SPaul Burton beqz t0, 2f 26*b2b135d9SPaul Burton 27*b2b135d9SPaul Burton /* Find the current physical GCR base address */ 28*b2b135d9SPaul Burton1: MFC0 t0, CP0_CMGCRBASE 29*b2b135d9SPaul Burton PTR_SLL t0, t0, 4 30*b2b135d9SPaul Burton 31*b2b135d9SPaul Burton /* If the GCRs are where we want, we're done */ 32*b2b135d9SPaul Burton PTR_LI t1, CONFIG_MIPS_CM_BASE 33*b2b135d9SPaul Burton beq t0, t1, 2f 34*b2b135d9SPaul Burton 35*b2b135d9SPaul Burton /* Move the GCRs to our configured base address */ 36*b2b135d9SPaul Burton PTR_LI t2, CKSEG1 37*b2b135d9SPaul Burton PTR_ADDU t0, t0, t2 38*b2b135d9SPaul Burton sw zero, GCR_BASE_UPPER(t0) 39*b2b135d9SPaul Burton sw t1, GCR_BASE(t0) 40*b2b135d9SPaul Burton 41*b2b135d9SPaul Burton /* Re-check the GCR base */ 42*b2b135d9SPaul Burton b 1b 43*b2b135d9SPaul Burton 44*b2b135d9SPaul Burton2: jr ra 45*b2b135d9SPaul Burton END(mips_cm_map) 46