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Searched refs:secondary (Results 1 – 25 of 34) sorted by relevance

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/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip_connector.c68 if (state->conn_state.secondary) { in rockchip_connector_pre_init()
111 if (state->conn_state.secondary) { in rockchip_connector_init()
112 conn = state->conn_state.secondary; in rockchip_connector_init()
156 if (state->conn_state.secondary) { in rockchip_connector_detect()
157 conn = state->conn_state.secondary; in rockchip_connector_detect()
176 if (state->conn_state.secondary) { in rockchip_connector_get_timing()
177 conn = state->conn_state.secondary; in rockchip_connector_get_timing()
197 if (state->conn_state.secondary) { in rockchip_connector_get_edid()
198 conn = state->conn_state.secondary; in rockchip_connector_get_edid()
229 if (state->conn_state.secondary) { in rockchip_connector_pre_enable()
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H A Drockchip_display.h257 struct rockchip_connector *secondary; member
H A Drockchip_lvds.c125 if (conn_state->secondary) in rockchip_lvds_connector_init()
H A Drockchip_display.c794 if (!ret && conn_state->secondary) { in display_init()
795 struct rockchip_connector *connector = conn_state->secondary; in display_init()
2464 s->conn_state.secondary = NULL; in rockchip_display_probe()
2467 s->conn_state.secondary = split_conn; in rockchip_display_probe()
H A Ddw_hdmi_qp.c1512 if (conn_state->secondary) in rockchip_dw_hdmi_qp_get_timing()
1513 _rockchip_dw_hdmi_qp_get_timing(conn_state->secondary, state); in rockchip_dw_hdmi_qp_get_timing()
/rk3399_rockchip-uboot/doc/
H A DREADME.arm6432 4. Spin-table is used to wake up secondary processors. One location
34 for secondary processors. It must be ensured that the location is
35 accessible and zero immediately after secondary processor
38 of secondary processors to it and send event to wakeup secondary
H A DREADME.mpc85xx-spin-table12 page translation for secondary cores to use this page of memory. Then 4KB
17 that secondary cores can see it.
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
H A DREADME.mpc85xxcds58 The U-Boot commands for copying the boot-bank into the secondary bank are
66 it into the secondary bank:
89 secondary bank as the boot-bank.
111 the "flinfo" command. The secondary bank is always FF00_0000.
H A DREADME.SPL7 To unify all existing implementations for a secondary program loader (SPL)
H A DREADME.davinci99 For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL)
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsocfpga_cyclone5.dtsi8 /* First 4KB has trampoline code for secondary cores. */
H A Dsocfpga_arria5.dtsi8 /* First 4KB has trampoline code for secondary cores. */
H A Dkeystone-k2e-netcp.dtsi151 secondary-slave-ports {
H A Dkeystone-k2l-netcp.dtsi150 secondary-slave-ports {
H A Dkeystone-k2hk-netcp.dtsi169 secondary-slave-ports {
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt35 The secondary index is the bit number within the RCC register bank, starting
65 The secondary index is bound with the following magic numbers:
/rk3399_rockchip-uboot/doc/mvebu/
H A Darmada-8k-memory.txt7 a single CP configuration, then all secondary-CP mappings are invalid.
/rk3399_rockchip-uboot/doc/uImage.FIT/
H A Dverified-boot.txt18 It is also possible to add a secondary signed firmware image, in read-write
81 use the secondary public key in the first-stage image to verify the second-
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A DKconfig33 - Bring secondary CPUs into U-Boot proper in a board specific
35 secondary CPUs will spin in unprotected memory area because the
/rk3399_rockchip-uboot/drivers/video/
H A Dipu.h29 struct clk *secondary; member
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/
H A Dpsci.S181 @ Set secondary boot entry
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc60 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
187 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
/rk3399_rockchip-uboot/arch/arm/mach-bcm283x/
H A DKconfig104 quiesce secondary SMP CPUs. This is not currently true in 64-bit
/rk3399_rockchip-uboot/board/davinci/da8xxevm/
H A DREADME.da85011 the secondary program loader (SPL). The SPL will initialize the system
/rk3399_rockchip-uboot/board/freescale/t4qds/
H A DREADME115 0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores

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