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Searched refs:reg_base (Results 1 – 25 of 40) sorted by relevance

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/rk3399_rockchip-uboot/drivers/spi/
H A Dcadence_qspi_apb.c165 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ argument
166 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
169 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ argument
170 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
186 void cadence_qspi_apb_controller_enable(void *reg_base) in cadence_qspi_apb_controller_enable() argument
189 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
191 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
194 void cadence_qspi_apb_controller_disable(void *reg_base) in cadence_qspi_apb_controller_disable() argument
197 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
199 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
[all …]
H A Dcadence_qspi.h68 void cadence_qspi_apb_chipselect(void *reg_base,
70 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
71 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
73 void cadence_qspi_apb_delay(void *reg_base,
77 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
78 void cadence_qspi_apb_readdata_capture(void *reg_base,
H A Datmel_spi.c250 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_claim_bus() local
270 writel(csrx, &reg_base->csr[cs]); in atmel_spi_claim_bus()
277 writel(mode, &reg_base->mr); in atmel_spi_claim_bus()
279 writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr); in atmel_spi_claim_bus()
329 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_xfer() local
371 readl(&reg_base->rdr); in atmel_spi_xfer()
375 status = readl(&reg_base->sr); in atmel_spi_xfer()
385 writel(value, &reg_base->tdr); in atmel_spi_xfer()
390 value = readl(&reg_base->rdr); in atmel_spi_xfer()
403 wait_for_bit_le32(&reg_base->sr, in atmel_spi_xfer()
/rk3399_rockchip-uboot/board/sunxi/
H A Dahci.c17 static int sunxi_ahci_phy_init(u8 *reg_base) in sunxi_ahci_phy_init() argument
22 writel(0, reg_base + AHCI_RWCR); in sunxi_ahci_phy_init()
25 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); in sunxi_ahci_phy_init()
26 clrsetbits_le32(reg_base + AHCI_PHYCS0R, in sunxi_ahci_phy_init()
29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()
32 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); in sunxi_ahci_phy_init()
33 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); in sunxi_ahci_phy_init()
34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); in sunxi_ahci_phy_init()
35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); in sunxi_ahci_phy_init()
38 setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in sunxi_ahci_phy_init()
[all …]
/rk3399_rockchip-uboot/drivers/mmc/
H A Dkona_sdhci.c82 void *reg_base; in kona_sdhci_init() local
92 reg_base = (void *)CONFIG_SYS_SDIO_BASE0; in kona_sdhci_init()
93 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, in kona_sdhci_init()
97 reg_base = (void *)CONFIG_SYS_SDIO_BASE1; in kona_sdhci_init()
98 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, in kona_sdhci_init()
102 reg_base = (void *)CONFIG_SYS_SDIO_BASE2; in kona_sdhci_init()
103 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, in kona_sdhci_init()
107 reg_base = (void *)CONFIG_SYS_SDIO_BASE3; in kona_sdhci_init()
108 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, in kona_sdhci_init()
122 host->ioaddr = reg_base; in kona_sdhci_init()
H A Ddavinci_mmc.c31 struct davinci_mmc_regs *regs = host->reg_base; in dmmc_set_clock()
131 volatile struct davinci_mmc_regs *regs = host->reg_base; in dmmc_send_cmd()
319 struct davinci_mmc_regs *regs = host->reg_base; in dmmc_init()
354 struct davinci_mmc_regs *regs = host->reg_base; in dmmc_set_ios()
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/
H A Dpll.h15 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
17 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
18 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
19 int uniphier_ld20_vpll27_init(unsigned long reg_base);
20 int uniphier_ld20_dspll_init(unsigned long reg_base);
H A Dpll-base-ld20.c31 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, in uniphier_ld20_sscpll_init() argument
37 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_init()
64 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) in uniphier_ld20_sscpll_ssc_en() argument
69 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_ssc_en()
82 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
87 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_set_regi()
101 int uniphier_ld20_vpll27_init(unsigned long reg_base) in uniphier_ld20_vpll27_init() argument
106 base = ioremap(reg_base, SZ_16); in uniphier_ld20_vpll27_init()
127 int uniphier_ld20_dspll_init(unsigned long reg_base) in uniphier_ld20_dspll_init() argument
132 base = ioremap(reg_base, SZ_16); in uniphier_ld20_dspll_init()
/rk3399_rockchip-uboot/drivers/usb/musb-new/
H A Dda8xx.c66 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt() local
79 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); in da8xx_musb_interrupt()
83 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); in da8xx_musb_interrupt()
99 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); in da8xx_musb_interrupt()
143 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); in da8xx_musb_interrupt()
153 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_init() local
174 musb_readb(reg_base, DA8XX_USB_CTRL_REG)); in da8xx_musb_init()
195 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable() local
202 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); in da8xx_musb_enable()
205 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, in da8xx_musb_enable()
[all …]
H A Dam35x.c95 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable() local
102 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); in am35x_musb_enable()
103 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); in am35x_musb_enable()
107 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, in am35x_musb_enable()
119 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable() local
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); in am35x_musb_disable()
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, in am35x_musb_disable()
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); in am35x_musb_disable()
227 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt() local
252 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); in am35x_musb_interrupt()
[all …]
H A Dmusb_dsps.c159 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable() local
167 dsps_writel(reg_base, wrp->epintr_set, epmask); in dsps_musb_enable()
168 dsps_writel(reg_base, wrp->coreintr_set, coremask); in dsps_musb_enable()
172 dsps_writel(reg_base, wrp->coreintr_set, in dsps_musb_enable()
189 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable() local
191 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); in dsps_musb_disable()
192 dsps_writel(reg_base, wrp->epintr_clear, in dsps_musb_disable()
195 dsps_writel(reg_base, wrp->eoi, 0); in dsps_musb_disable()
296 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt() local
312 epintr = dsps_readl(reg_base, wrp->epintr_status); in dsps_interrupt()
[all …]
/rk3399_rockchip-uboot/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c26 struct atmel_pio4_port *reg_base; member
100 (struct atmel_pio4_port *)((u32)plat->reg_base + in atmel_pio4_bank_base()
165 plat->reg_base = (struct atmel_pio4_port *)addr_base; in atmel_pinctrl_probe()
/rk3399_rockchip-uboot/drivers/clk/at91/
H A Dpmc.c42 plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev); in at91_pmc_core_probe()
117 plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev_pmc); in at91_clk_probe()
H A Dpmc.h12 struct at91_pmc *reg_base; member
H A Dclk-main.c20 struct at91_pmc *pmc = plat->reg_base; in main_osc_clk_enable()
H A Dclk-plla.c20 struct at91_pmc *pmc = plat->reg_base; in plla_clk_enable()
H A Dclk-h32mx.c23 struct at91_pmc *pmc = plat->reg_base; in sama5d4_h32mx_clk_get_rate()
H A Dclk-generated.c52 struct at91_pmc *pmc = plat->reg_base; in generic_clk_get_rate()
79 struct at91_pmc *pmc = plat->reg_base; in generic_clk_set_rate()
H A Dclk-utmi.c22 struct at91_pmc *pmc = plat->reg_base; in utmi_clk_enable()
H A Dclk-system.c50 struct at91_pmc *pmc = plat->reg_base; in system_clk_enable()
H A Dclk-peripheral.c58 struct at91_pmc *pmc = plat->reg_base; in periph_clk_enable()
/rk3399_rockchip-uboot/drivers/pci/
H A Dpci_ftpci100.c20 unsigned int reg_base; member
229 priv->reg_base = CONFIG_FTPCI100_BASE; in ftpci_preinit()
234 ftpci100 = (struct ftpci100_ahbc *)priv->reg_base; in ftpci_preinit()
/rk3399_rockchip-uboot/drivers/gpio/
H A Datmel_pio4.c179 struct atmel_pio4_port *reg_base; member
187 (struct atmel_pio4_port *)((u32)plat->reg_base + in atmel_pio4_bank_base()
305 plat->reg_base = (struct atmel_pio4_port *)addr_base; in atmel_pio4_probe()
/rk3399_rockchip-uboot/drivers/rknand/
H A Drknand.h60 int rk_ftl_init(u32 *reg_base);
/rk3399_rockchip-uboot/drivers/crypto/rockchip/
H A Drkce_core.c288 void *rkce_hardware_alloc(void __iomem *reg_base) in rkce_hardware_alloc() argument
292 rk_debug("reg_base = %p", reg_base); in rkce_hardware_alloc()
294 if (!reg_base) in rkce_hardware_alloc()
301 hardware->rkce_reg = reg_base; in rkce_hardware_alloc()

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