xref: /rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/pll.h (revision d38de7cb03adf88e18c05d840c2528b7a5af2f9b)
16a3e4274SMasahiro Yamada /*
26a3e4274SMasahiro Yamada  * Copyright (C) 2016 Socionext Inc.
36a3e4274SMasahiro Yamada  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
46a3e4274SMasahiro Yamada  *
56a3e4274SMasahiro Yamada  * SPDX-License-Identifier:	GPL-2.0+
66a3e4274SMasahiro Yamada  */
76a3e4274SMasahiro Yamada 
86a3e4274SMasahiro Yamada #ifndef MACH_PLL_H
96a3e4274SMasahiro Yamada #define MACH_PLL_H
106a3e4274SMasahiro Yamada 
11682e09ffSMasahiro Yamada #define UNIPHIER_PLL_FREQ_DEFAULT	(0)
12682e09ffSMasahiro Yamada 
136a3e4274SMasahiro Yamada void uniphier_ld4_dpll_ssc_en(void);
146a3e4274SMasahiro Yamada 
15682e09ffSMasahiro Yamada int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
16682e09ffSMasahiro Yamada 			      unsigned int ssc_rate, unsigned int divn);
17682e09ffSMasahiro Yamada int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
18*bc647958SMasahiro Yamada int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
19682e09ffSMasahiro Yamada int uniphier_ld20_vpll27_init(unsigned long reg_base);
20682e09ffSMasahiro Yamada int uniphier_ld20_dspll_init(unsigned long reg_base);
21682e09ffSMasahiro Yamada 
226a3e4274SMasahiro Yamada #endif /* MACH_PLL_H */
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