| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | mp.c | 49 out_be32(&pic->pir, 1 << nr); in cpu_reset()
51 (void)in_be32(&pic->pir); in cpu_reset()
52 out_be32(&pic->pir, 0x0); in cpu_reset()
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 232 writel(0x00000003, &mctl_phy->pir); in mctl_init()
240 writel(0x000005f3, &mctl_phy->pir); in mctl_init()
248 writel(0x5f3, &mctl_phy->pir); in mctl_init()
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| H A D | dram_sun6i.c | 160 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
161 writel(MCTL_PIR_STEP1, &mctl_phy->pir); in mctl_channel_init()
191 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
192 writel(MCTL_PIR_STEP2, &mctl_phy->pir); in mctl_channel_init()
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| H A D | dram_sunxi_dw.c | 24 writel(val | PIR_INIT, &mctl_ctl->pir); in mctl_phy_init()
287 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
314 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
320 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
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| H A D | dram_sun9i.c | 753 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x20df3); in mctl_channel_init()
755 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x2c573); in mctl_channel_init()
760 while ((readl(&mctl_phy->pir) & MCTL_PIR_INIT) != MCTL_PIR_INIT) { in mctl_channel_init()
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| H A D | dram_sun8i_a33.c | 176 writel(val, &mctl_ctl->pir); in mctl_set_pir()
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| H A D | dram_sun8i_a83t.c | 208 writel(val, &mctl_ctl->pir); in mctl_set_pir()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/ |
| H A D | sdram_rk3066.c | 162 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
171 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
292 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
320 setbits_le32(&publ->pir, in memory_init()
426 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
429 setbits_le32(&publ->pir, in data_training()
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 162 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
171 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
303 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
331 setbits_le32(&publ->pir, in memory_init()
439 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
442 setbits_le32(&publ->pir, in data_training()
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| H A D | sdram_rk3288.c | 161 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
170 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
361 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
389 setbits_le32(&publ->pir, in memory_init()
497 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
500 setbits_le32(&publ->pir, in data_training()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a33.h | 67 u32 pir; /* 0x00 */ member
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| H A D | dram_sunxi_dw.h | 83 u32 pir; /* 0x00 PHY initialization register */ member
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| H A D | dram_sun8i_a83t.h | 67 u32 pir; /* 0x00 */ member
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| H A D | dram_sun9i.h | 95 u32 pir; /* 0x04 PHY initialisation register */ member
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| H A D | dram_sun8i_a23.h | 165 u32 pir; /* 0x04 */ member
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| H A D | dram_sun6i.h | 159 u32 pir; /* 0x04 */ member
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | ddr_rk3288.h | 169 u32 pir; member
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | stm32_qspi.c | 36 u32 pir; /* 0x2C */ member
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| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | immap_86xx.h | 547 uint pir; /* 0x41090 - Processor Initialization Register */ member
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| H A D | immap_85xx.h | 648 u32 pir; /* Processor Initialization */ member
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