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1b48bbdd |
| 21-Nov-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
UPSTREAM: bitops: collect BIT macros to include/linux/bitops.h
Same macros are defined in various places. Collect them into
include/linux/bitops.h like Linux.
Change-Id: I81d12e8c8151c6eb29499d2b5
UPSTREAM: bitops: collect BIT macros to include/linux/bitops.h
Same macros are defined in various places. Collect them into
include/linux/bitops.h like Linux.
Change-Id: I81d12e8c8151c6eb29499d2b5cd61ed782500492
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit ed3986ca30972c94f0076f88c948406ce030a05c)
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| #
f6457ce5 |
| 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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f43a0099 |
| 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: Rename bus-width related macros in H3 DRAM code
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.
As H3 itself come with 32-bit D
sunxi: Rename bus-width related macros in H3 DRAM code
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.
As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit and 16-bit.
Rename the bit's macro, and also rename the variable name in
dram_sun8i_h3.c.
This commit do not add 16-bit DRAM controller support, but the support
will be introduced in next commit.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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| #
9934aba4 |
| 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: makes an invisible option for H3-like DRAM controllers
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initial
sunxi: makes an invisible option for H3-like DRAM controllers
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.
Add a invisible option for easier DRAM initialization code reuse.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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