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Searched refs:phyaddr (Results 1 – 25 of 36) sorted by relevance

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/rk3399_rockchip-uboot/board/zyxel/nsa310s/
H A Dnsa310s.c86 u16 phyaddr; in reset_phy() local
93 if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) { in reset_phy()
99 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); in reset_phy()
100 miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg); in reset_phy()
102 miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg); in reset_phy()
103 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); in reset_phy()
106 if (miiphy_reset(name, phyaddr)) in reset_phy()
115 miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); in reset_phy()
117 miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg); in reset_phy()
122 miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg); in reset_phy()
[all …]
/rk3399_rockchip-uboot/board/LaCie/common/
H A Dcommon.c21 void mv_phy_88e1116_init(const char *name, u16 phyaddr) in mv_phy_88e1116_init() argument
32 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2); in mv_phy_88e1116_init()
33 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg); in mv_phy_88e1116_init()
35 miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); in mv_phy_88e1116_init()
36 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0); in mv_phy_88e1116_init()
38 if (miiphy_reset(name, phyaddr) == 0) in mv_phy_88e1116_init()
42 void mv_phy_88e1318_init(const char *name, u16 phyaddr) in mv_phy_88e1318_init() argument
52 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3); in mv_phy_88e1318_init()
53 miiphy_read(name, phyaddr, 16, &reg); in mv_phy_88e1318_init()
55 miiphy_write(name, phyaddr, 16, reg); in mv_phy_88e1318_init()
[all …]
H A Dcommon.h11 void mv_phy_88e1116_init(const char *name, u16 phyaddr);
12 void mv_phy_88e1318_init(const char *name, u16 phyaddr);
/rk3399_rockchip-uboot/drivers/net/
H A Dmcfmii.c138 int phyaddr, pass; in mii_discover_phy() local
145 phyaddr = -1; /* didn't find a PHY yet */ in mii_discover_phy()
146 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { in mii_discover_phy()
156 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { in mii_discover_phy()
164 phyaddr = phyno; in mii_discover_phy()
199 if (phyaddr < 0) in mii_discover_phy()
202 return phyaddr; in mii_discover_phy()
H A Dxilinx_emaclite.c91 int phyaddr; member
266 if (emaclite->phyaddr != -1) { in setup_phy()
267 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); in setup_phy()
272 emaclite->phyaddr); in setup_phy()
275 emaclite->phyaddr); in setup_phy()
276 emaclite->phyaddr = -1; in setup_phy()
280 if (emaclite->phyaddr == -1) { in setup_phy()
287 emaclite->phyaddr = i; in setup_phy()
296 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, in setup_phy()
605 emaclite->phyaddr = -1; in emaclite_ofdata_to_platdata()
[all …]
H A Dxilinx_ll_temac.c48 unsigned int phyaddr; member
269 phydev = phy_connect(ll_temac->bus, ll_temac->phyaddr, in ll_temac_phy_init()
343 if (devinf->phyaddr == -1) in xilinx_ll_temac_initialize()
344 ll_temac->phyaddr = ll_temac_phy_addr(ll_temac->bus); in xilinx_ll_temac_initialize()
346 ll_temac->phyaddr = devinf->phyaddr; in xilinx_ll_temac_initialize()
372 devinf.phyaddr = -1; in xilinx_ll_temac_eth_init()
H A Dzynq_gem.c177 int phyaddr; member
249 if (priv->phyaddr != -1) { in phy_detection()
250 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); in phy_detection()
255 priv->phyaddr); in phy_detection()
259 priv->phyaddr); in phy_detection()
260 priv->phyaddr = -1; in phy_detection()
265 if (priv->phyaddr == -1) { in phy_detection()
272 priv->phyaddr = i; in phy_detection()
335 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, in zynq_phy_init()
683 priv->phyaddr = -1; in zynq_gem_ofdata_to_platdata()
[all …]
H A Dbcm-sf2-eth.h53 int (*miiphy_read)(struct mii_dev *bus, int phyaddr, int devad,
55 int (*miiphy_write)(struct mii_dev *bus, int phyaddr, int devad,
H A Dxilinx_axi_emac.c87 int phyaddr; member
238 if (priv->phyaddr == -1) { in axiemac_phy_init()
245 priv->phyaddr = i; in axiemac_phy_init()
254 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); in axiemac_phy_init()
279 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp); in setup_phy()
284 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp); in setup_phy()
713 priv->phyaddr = -1; in axi_emac_ofdata_to_platdata()
717 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); in axi_emac_ofdata_to_platdata()
729 priv->phyaddr, phy_string_for_interface(priv->interface)); in axi_emac_ofdata_to_platdata()
H A Dmpc8xx_fec.c756 int phyaddr; in mii_discover_phy() local
758 phyaddr = -1; /* didn't find a PHY yet */ in mii_discover_phy()
759 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { in mii_discover_phy()
768 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { in mii_discover_phy()
771 phyaddr = phyno; in mii_discover_phy()
777 if (phyaddr < 0) in mii_discover_phy()
780 return phyaddr; in mii_discover_phy()
H A Dax88180.c259 unsigned short phyaddr; in ax88180_phy_initial() local
263 phyaddr = CONFIG_PHY_ADDR; in ax88180_phy_initial()
265 for (phyaddr = 0; phyaddr < 32; ++phyaddr) in ax88180_phy_initial()
268 priv->PhyAddr = phyaddr; in ax88180_phy_initial()
H A Dfec_mxc.c89 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, in fec_mdio_read() argument
103 phy = phyaddr << FEC_MII_DATA_PA_SHIFT; in fec_mdio_read()
122 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, in fec_mdio_read()
154 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr, in fec_mdio_write() argument
162 phy = phyaddr << FEC_MII_DATA_PA_SHIFT; in fec_mdio_write()
178 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, in fec_mdio_write()
184 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr, in fec_phy_read() argument
187 return fec_mdio_read(bus->priv, phyaddr, regaddr); in fec_phy_read()
190 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr, in fec_phy_write() argument
193 return fec_mdio_write(bus->priv, phyaddr, regaddr, data); in fec_phy_write()
H A Dftmac110.c69 uint8_t phyaddr, uint8_t phyreg) in mdio_read() argument
77 | (phyaddr << PHYCR_ADDR_SHIFT) in mdio_read()
98 uint8_t phyaddr, uint8_t phyreg, uint16_t phydata) in mdio_write() argument
105 | (phyaddr << PHYCR_ADDR_SHIFT) in mdio_write()
H A Dbcm-sf2-eth-gmac.c606 int gmac_miiphy_read(struct mii_dev *bus, int phyaddr, int devad, int reg) in gmac_miiphy_read() argument
619 tmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) | in gmac_miiphy_read()
621 debug("MII read cmd 0x%x, phy 0x%x, reg 0x%x\n", tmp, phyaddr, reg); in gmac_miiphy_read()
634 int gmac_miiphy_write(struct mii_dev *bus, int phyaddr, int devad, int reg, in gmac_miiphy_write() argument
647 tmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) | in gmac_miiphy_write()
650 tmp, phyaddr, reg, value); in gmac_miiphy_write()
H A Dsmc91111.c892 byte phyaddr = SMC_PHY_ADDR; in smc_read_phy_register() local
909 if (phyaddr & mask) in smc_read_phy_register()
988 phyaddr, phyreg, phydata); in smc_read_phy_register()
1008 byte phyaddr = SMC_PHY_ADDR; in smc_write_phy_register() local
1025 if (phyaddr & mask) in smc_write_phy_register()
1100 phyaddr, phyreg, phydata); in smc_write_phy_register()
H A Dsun8i_emac.c118 u32 phyaddr; member
264 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT; in sun8i_emac_set_syscon_ephy()
321 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); in sun8i_phy_init()
783 priv->phyaddr = -1; in sun8i_emac_eth_ofdata_to_platdata()
789 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", in sun8i_emac_eth_ofdata_to_platdata()
H A Ddwc_eth_qos.h66 int phyaddr; member
H A Dtsec.c39 .phyaddr = FEC_PHY_ADDR,
668 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, in init_phy()
709 priv->phyaddr = tsec_info->phyaddr; in tsec_initialize()
790 priv->phyaddr = reg; in tsec_probe()
H A Dmvneta.c284 int phyaddr; member
577 return pp->phyaddr > PHY_MAX_ADDR; in mvneta_port_is_fixed_link()
1553 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); in mvneta_start()
1555 phydev = phy_connect(pp->bus, pp->phyaddr, dev, in mvneta_start()
1710 pp->phyaddr = PHY_MAX_ADDR + 1; in mvneta_probe()
1717 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); in mvneta_probe()
/rk3399_rockchip-uboot/drivers/net/phy/
H A Dmv88e6352.c236 u16 value = 0, phyaddr, reg, port; in do_mvsw_reg_read() local
239 phyaddr = simple_strtoul(argv[1], NULL, 10); in do_mvsw_reg_read()
243 ret = sw_reg_read(name, phyaddr, port, reg, &value); in do_mvsw_reg_read()
251 u16 value = 0, phyaddr, reg, port; in do_mvsw_reg_write() local
254 phyaddr = simple_strtoul(argv[1], NULL, 10); in do_mvsw_reg_write()
259 ret = sw_reg_write(name, phyaddr, port, reg, value); in do_mvsw_reg_write()
/rk3399_rockchip-uboot/board/freescale/common/
H A Dsgmii_riser.c28 tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET; in fsl_sgmii_riser_init()
119 priv->phyaddr); in fsl_sgmii_riser_fdt_fixup()
/rk3399_rockchip-uboot/include/
H A Dtsec.h54 .phyaddr = TSEC##num##_PHY_ADDR, \
64 x.phyaddr = TSEC##num##_PHY_ADDR; \
404 uint phyaddr; member
423 unsigned int phyaddr; member
/rk3399_rockchip-uboot/board/freescale/mpc8536ds/
H A Dmpc8536ds.c237 tsec_info[num].phyaddr = 0; in board_eth_init()
246 tsec_info[num].phyaddr = 1; in board_eth_init()
/rk3399_rockchip-uboot/board/freescale/mpc837xemds/
H A Dmpc837xemds.c108 tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII; in board_eth_init()
126 tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; in board_eth_init()
/rk3399_rockchip-uboot/drivers/net/fm/
H A Dfm.h129 int phyaddr; member

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