1*f1df81c4SGerald Kerma /*
2*f1df81c4SGerald Kerma * Copyright (C) 2015
3*f1df81c4SGerald Kerma * Gerald Kerma <dreagle@doukki.net>
4*f1df81c4SGerald Kerma * Tony Dinh <mibodhi@gmail.com>
5*f1df81c4SGerald Kerma *
6*f1df81c4SGerald Kerma * SPDX-License-Identifier: GPL-2.0+
7*f1df81c4SGerald Kerma */
8*f1df81c4SGerald Kerma
9*f1df81c4SGerald Kerma #include <common.h>
10*f1df81c4SGerald Kerma #include <miiphy.h>
11*f1df81c4SGerald Kerma #include <asm/arch/cpu.h>
12*f1df81c4SGerald Kerma #include <asm/arch/soc.h>
13*f1df81c4SGerald Kerma #include <asm/arch/mpp.h>
14*f1df81c4SGerald Kerma #include <asm/io.h>
15*f1df81c4SGerald Kerma #include "nsa310s.h"
16*f1df81c4SGerald Kerma
17*f1df81c4SGerald Kerma DECLARE_GLOBAL_DATA_PTR;
18*f1df81c4SGerald Kerma
board_early_init_f(void)19*f1df81c4SGerald Kerma int board_early_init_f(void)
20*f1df81c4SGerald Kerma {
21*f1df81c4SGerald Kerma /*
22*f1df81c4SGerald Kerma * default gpio configuration
23*f1df81c4SGerald Kerma * There are maximum 64 gpios controlled through 2 sets of registers
24*f1df81c4SGerald Kerma * the below configuration configures mainly initial LED status
25*f1df81c4SGerald Kerma */
26*f1df81c4SGerald Kerma mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
27*f1df81c4SGerald Kerma NSA310S_OE_LOW, NSA310S_OE_HIGH);
28*f1df81c4SGerald Kerma
29*f1df81c4SGerald Kerma /* (all LEDs & power off active high) */
30*f1df81c4SGerald Kerma /* Multi-Purpose Pins Functionality configuration */
31*f1df81c4SGerald Kerma static const u32 kwmpp_config[] = {
32*f1df81c4SGerald Kerma MPP0_NF_IO2,
33*f1df81c4SGerald Kerma MPP1_NF_IO3,
34*f1df81c4SGerald Kerma MPP2_NF_IO4,
35*f1df81c4SGerald Kerma MPP3_NF_IO5,
36*f1df81c4SGerald Kerma MPP4_NF_IO6,
37*f1df81c4SGerald Kerma MPP5_NF_IO7,
38*f1df81c4SGerald Kerma MPP6_SYSRST_OUTn,
39*f1df81c4SGerald Kerma MPP7_GPO,
40*f1df81c4SGerald Kerma MPP8_TW_SDA,
41*f1df81c4SGerald Kerma MPP9_TW_SCK,
42*f1df81c4SGerald Kerma MPP10_UART0_TXD,
43*f1df81c4SGerald Kerma MPP11_UART0_RXD,
44*f1df81c4SGerald Kerma MPP12_GPO,
45*f1df81c4SGerald Kerma MPP13_GPIO,
46*f1df81c4SGerald Kerma MPP14_GPIO,
47*f1df81c4SGerald Kerma MPP15_GPIO,
48*f1df81c4SGerald Kerma MPP16_GPIO,
49*f1df81c4SGerald Kerma MPP17_GPIO,
50*f1df81c4SGerald Kerma MPP18_NF_IO0,
51*f1df81c4SGerald Kerma MPP19_NF_IO1,
52*f1df81c4SGerald Kerma MPP20_GPIO,
53*f1df81c4SGerald Kerma MPP21_GPIO,
54*f1df81c4SGerald Kerma MPP22_GPIO,
55*f1df81c4SGerald Kerma MPP23_GPIO,
56*f1df81c4SGerald Kerma MPP24_GPIO,
57*f1df81c4SGerald Kerma MPP25_GPIO,
58*f1df81c4SGerald Kerma MPP26_GPIO,
59*f1df81c4SGerald Kerma MPP27_GPIO,
60*f1df81c4SGerald Kerma MPP28_GPIO,
61*f1df81c4SGerald Kerma MPP29_GPIO,
62*f1df81c4SGerald Kerma MPP30_GPIO,
63*f1df81c4SGerald Kerma MPP31_GPIO,
64*f1df81c4SGerald Kerma MPP32_GPIO,
65*f1df81c4SGerald Kerma MPP33_GPIO,
66*f1df81c4SGerald Kerma MPP34_GPIO,
67*f1df81c4SGerald Kerma MPP35_GPIO,
68*f1df81c4SGerald Kerma 0
69*f1df81c4SGerald Kerma };
70*f1df81c4SGerald Kerma kirkwood_mpp_conf(kwmpp_config, NULL);
71*f1df81c4SGerald Kerma return 0;
72*f1df81c4SGerald Kerma }
73*f1df81c4SGerald Kerma
board_init(void)74*f1df81c4SGerald Kerma int board_init(void)
75*f1df81c4SGerald Kerma {
76*f1df81c4SGerald Kerma /* address of boot parameters */
77*f1df81c4SGerald Kerma gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
78*f1df81c4SGerald Kerma
79*f1df81c4SGerald Kerma return 0;
80*f1df81c4SGerald Kerma }
81*f1df81c4SGerald Kerma
82*f1df81c4SGerald Kerma #ifdef CONFIG_RESET_PHY_R
reset_phy(void)83*f1df81c4SGerald Kerma void reset_phy(void)
84*f1df81c4SGerald Kerma {
85*f1df81c4SGerald Kerma u16 reg;
86*f1df81c4SGerald Kerma u16 phyaddr;
87*f1df81c4SGerald Kerma char *name = "egiga0";
88*f1df81c4SGerald Kerma
89*f1df81c4SGerald Kerma if (miiphy_set_current_dev(name))
90*f1df81c4SGerald Kerma return;
91*f1df81c4SGerald Kerma
92*f1df81c4SGerald Kerma /* read PHY dev address */
93*f1df81c4SGerald Kerma if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
94*f1df81c4SGerald Kerma printf("could not read PHY dev address\n");
95*f1df81c4SGerald Kerma return;
96*f1df81c4SGerald Kerma }
97*f1df81c4SGerald Kerma
98*f1df81c4SGerald Kerma /* set RGMII delay */
99*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
100*f1df81c4SGerald Kerma miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
101*f1df81c4SGerald Kerma reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
102*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
103*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
104*f1df81c4SGerald Kerma
105*f1df81c4SGerald Kerma /* reset PHY */
106*f1df81c4SGerald Kerma if (miiphy_reset(name, phyaddr))
107*f1df81c4SGerald Kerma return;
108*f1df81c4SGerald Kerma
109*f1df81c4SGerald Kerma /*
110*f1df81c4SGerald Kerma * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
111*f1df81c4SGerald Kerma * and has an MCU attached to the LED[2] via tristate interrupt
112*f1df81c4SGerald Kerma */
113*f1df81c4SGerald Kerma
114*f1df81c4SGerald Kerma /* switch to LED register page */
115*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
116*f1df81c4SGerald Kerma /* read out LED polarity register */
117*f1df81c4SGerald Kerma miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
118*f1df81c4SGerald Kerma /* clear 4, set 5 - LED2 low, tri-state */
119*f1df81c4SGerald Kerma reg &= ~(MV88E1318_LED2_4);
120*f1df81c4SGerald Kerma reg |= (MV88E1318_LED2_5);
121*f1df81c4SGerald Kerma /* write back LED polarity register */
122*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
123*f1df81c4SGerald Kerma /* jump back to page 0, per the PHY chip documenation. */
124*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
125*f1df81c4SGerald Kerma
126*f1df81c4SGerald Kerma /* set PHY back to auto-negotiation mode */
127*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, 0x4, 0x1e1);
128*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, 0x9, 0x300);
129*f1df81c4SGerald Kerma /* downshift */
130*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, 0x10, 0x3860);
131*f1df81c4SGerald Kerma miiphy_write(name, phyaddr, 0x0, 0x9140);
132*f1df81c4SGerald Kerma }
133*f1df81c4SGerald Kerma #endif /* CONFIG_RESET_PHY_R */
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