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Searched refs:phy_read (Results 1 – 25 of 46) sorted by relevance

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/rk3399_rockchip-uboot/drivers/net/phy/
H A Dgeneric_10g.c43 phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
44 reg = phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
60 stat2 = phy_read(phydev, mmd, MDIO_STAT2); in gen10g_discover_mmds()
66 devs1 = phy_read(phydev, mmd, MDIO_DEVS1); in gen10g_discover_mmds()
67 devs2 = phy_read(phydev, mmd, MDIO_DEVS2); in gen10g_discover_mmds()
H A Dvitesse.c89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
149 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL); in vsc8601_add_skew()
177 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); in vsc8574_config()
194 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); in vsc8574_config()
197 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18); in vsc8574_config()
202 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON); in vsc8574_config()
222 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19); in vsc8514_config()
237 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); in vsc8514_config()
240 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); in vsc8514_config()
250 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23); in vsc8514_config()
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H A Dmscc.c149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
177 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
183 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
204 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_AUX_CNTRL_STAT_REG); in mscc_parse_status()
253 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
256 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
259 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
314 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
326 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, in vsc8531_vsc8541_mac_config()
[all …]
H A Dmarvell.c134 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); in m88e1xxx_parse_status()
152 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
203 reg = phy_read(phydev, in m88e1111s_config()
219 reg = phy_read(phydev, in m88e1111s_config()
234 reg = phy_read(phydev, in m88e1111s_config()
246 reg = phy_read(phydev, in m88e1111s_config()
252 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
263 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
295 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); in m88e1518_phy_writebits()
344 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1518_config()
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H A Daquantia.c24 u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
69 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
70 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
76 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
88 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
89 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1); in aquantia_startup()
95 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_startup()
H A Dphy.c49 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
82 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
94 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
157 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
196 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
229 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
264 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
270 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
292 int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_parse_link()
306 gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); in genphy_parse_link()
[all …]
H A Drealtek.c77 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in rtl8211x_config()
85 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); in rtl8211x_config()
100 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11); in rtl8211f_config()
131 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS); in rtl8211x_parse_status()
150 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211x_parse_status()
190 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS); in rtl8211f_parse_status()
203 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_parse_status()
H A Drockchip-fephy.c72 return phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD1); in rockchip_fephy_group_read()
74 return (phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD1) | in rockchip_fephy_group_read()
75 (phy_read(phydev, MDIO_DEVAD_NONE, SMI_ADDR_TSTREAD2) << 16)); in rockchip_fephy_group_read()
100 phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in rockchip_fephy_startup()
H A Det1011c.c31 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
47 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
58 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
H A Dbroadcom.c46 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
70 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); in bcm54xx_parse_status()
130 return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; in bcm5482_read_wirespeed()
138 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
237 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); in bcm5482_is_serdes()
273 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); in bcm5482_parse_serdes_sr()
H A Dxilinx_phy.c50 status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in xilinxphy_startup()
72 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
121 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_config()
H A Dnatsemi.c24 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
68 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); in dp83865_parse_status()
121 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in dp83848_parse_status()
H A Dteranetics.c31 phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf; in tn2020_config()
58 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT); in tn2020_startup()
H A Datheros.c62 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8035_config()
66 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8035_config()
H A Dmicrel_ksz90x1.c54 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()
232 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); in ksz9021_phy_extended_read()
317 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA); in ksz9031_phy_extended_read()
357 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in ksz9031_config()
H A Dti.c131 value = phy_read(phydev, addr, MII_MMD_DATA); in phy_read_mmd_indirect()
232 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); in dp83867_config()
246 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2); in dp83867_config()
H A Dmicrel_ksz8xxx.c37 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); in ksz_genconfig_bcastoff()
70 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); in ksz8051_config()
H A Dlxt.c26 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_LXT971_SR2); in lxt971_parse_status()
H A Drk630phy.c132 phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in rk630_phy_startup()
140 phy_read(phydev, MDIO_DEVAD_NONE, 0) & ~BIT(13)); in rk630_phy_s40_config_init()
H A Ddavicom.c46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
/rk3399_rockchip-uboot/board/spear/x600/
H A Dx600.c77 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
78 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
/rk3399_rockchip-uboot/board/Marvell/db-mv784mp-gp/
H A Ddb-mv784mp-gp.c103 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); in board_phy_config()
112 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); in board_phy_config()
/rk3399_rockchip-uboot/board/gdsys/a38x/
H A Dihs_phys.c33 reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); in ihs_phy_config()
41 reg = phy_read(phydev, MDIO_DEVAD_NONE, 26); in ihs_phy_config()
51 reg = phy_read(phydev, MDIO_DEVAD_NONE, 4); in ihs_phy_config()
54 reg = phy_read(phydev, MDIO_DEVAD_NONE, 9); in ihs_phy_config()
59 reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); in ihs_phy_config()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dinno_video_phy.c89 static inline u32 phy_read(struct inno_video_phy *inno, u32 reg) in phy_read() function
99 orig = phy_read(inno, reg); in phy_update_bits()
/rk3399_rockchip-uboot/include/
H A Dphy.h162 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) in phy_read() function
206 return phy_read(phydev, devad, regnum); in phy_read_mmd()
212 return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA); in phy_read_mmd()

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