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Searched refs:phy_base (Results 1 – 17 of 17) sorted by relevance

/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c13 static void sdram_phy_dll_bypass_set(void __iomem *phy_base, u32 freq) in sdram_phy_dll_bypass_set() argument
19 setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); in sdram_phy_dll_bypass_set()
20 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); in sdram_phy_dll_bypass_set()
23 setbits_le32(PHY_REG(phy_base, j), 1 << 4); in sdram_phy_dll_bypass_set()
24 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); in sdram_phy_dll_bypass_set()
29 setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
31 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
46 writel(tmp, PHY_REG(phy_base, j)); in sdram_phy_dll_bypass_set()
50 static void sdram_phy_set_ds_odt(void __iomem *phy_base, in sdram_phy_set_ds_odt() argument
71 writel(cmd_drv, PHY_REG(phy_base, 0x11)); in sdram_phy_set_ds_odt()
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H A Dsdram_rv1126.c566 void __iomem *phy_base = dram->phy; in phy_pll_set() local
571 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); in phy_pll_set()
572 while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) { in phy_pll_set()
596 writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); in phy_pll_set()
597 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, in phy_pll_set()
599 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, in phy_pll_set()
602 clrsetbits_le32(PHY_REG(phy_base, 0x52), in phy_pll_set()
604 clrsetbits_le32(PHY_REG(phy_base, 0x53), in phy_pll_set()
886 void __iomem *phy_base = dram->phy; in set_ds_odt() local
1043 clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); in set_ds_odt()
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H A Dsdram_rk3328.c123 void __iomem *phy_base = dram->phy; in rkclk_configure_ddr() local
126 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); in rkclk_configure_ddr()
263 void __iomem *phy_base = dram->phy; in rx_deskew_switch_adjust() local
266 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); in rx_deskew_switch_adjust()
270 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); in rx_deskew_switch_adjust()
271 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, in rx_deskew_switch_adjust()
277 void __iomem *phy_base = dram->phy; in tx_deskew_switch_adjust() local
279 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); in tx_deskew_switch_adjust()
H A Dsdram_px30.c241 void __iomem *phy_base = dram->phy; in check_rd_gate() local
248 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; in check_rd_gate()
263 gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); in check_rd_gate()
359 void __iomem *phy_base = dram->phy; in enable_low_power() local
386 setbits_le32(PHY_REG(phy_base, 7), 1 << 7); in enable_low_power()
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/dram/
H A Dddrphy-ld4.c31 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) in uniphier_ld4_ddrphy_init() argument
48 writel(0x0300c473, phy_base + PHY_PGCR1); in uniphier_ld4_ddrphy_init()
49 writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); in uniphier_ld4_ddrphy_init()
50 writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1); in uniphier_ld4_ddrphy_init()
51 writel(0x00083DEF, phy_base + PHY_PTR2); in uniphier_ld4_ddrphy_init()
52 writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3); in uniphier_ld4_ddrphy_init()
53 writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4); in uniphier_ld4_ddrphy_init()
54 writel(0xF004001A, phy_base + PHY_DSGCR); in uniphier_ld4_ddrphy_init()
57 tmp = readl(phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
60 writel(tmp, phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
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H A Dumc-pxs2.c58 static void ddrphy_fifo_reset(void __iomem *phy_base) in ddrphy_fifo_reset() argument
62 tmp = readl(phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
64 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
69 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
74 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) in ddrphy_vt_ctrl() argument
78 tmp = readl(phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
85 writel(tmp, phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
88 while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP)) in ddrphy_vt_ctrl()
93 static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step) in ddrphy_dqs_delay_fixup() argument
97 void __iomem *dx_base = phy_base + MPHY_DX_BASE; in ddrphy_dqs_delay_fixup()
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H A Dddrphy-training.c18 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
20 void __iomem *dx_base = phy_base + PHY_DX_BASE; in ddrphy_prepare_training()
34 tmp = readl(phy_base + PHY_DTCR); in ddrphy_prepare_training()
43 writel(tmp, phy_base + PHY_DTCR); in ddrphy_prepare_training()
104 int ddrphy_training(void __iomem *phy_base) in ddrphy_training() argument
120 writel(init_flag, phy_base + PHY_PIR); in ddrphy_training()
129 pgsr0 = readl(phy_base + PHY_PGSR0); in ddrphy_training()
H A Dddrphy-init.h13 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
14 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
15 int ddrphy_training(void __iomem *phy_base);
H A Dcmd_ddrmphy.c72 void __iomem *phy_base, *dx_base; in dump_loop() local
76 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
77 dx_base = phy_base + MPHY_DX_BASE; in dump_loop()
86 iounmap(phy_base); in dump_loop()
92 void __iomem *phy_base, *zq_base; in zq_dump() local
100 phy_base = ioremap(param->phy[phy].base, SZ_4K); in zq_dump()
101 zq_base = phy_base + MPHY_ZQ_BASE; in zq_dump()
122 iounmap(phy_base); in zq_dump()
228 { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
235 void __iomem *reg = phy_base + ofst; \
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H A Dcmd_ddrphy.c87 void __iomem *phy_base, *dx_base; in dump_loop() local
91 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
92 dx_base = phy_base + PHY_DX_BASE; in dump_loop()
101 iounmap(phy_base); in dump_loop()
202 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
210 void __iomem *reg = phy_base + ofst; \
217 void __iomem *phy_base; in reg_dump() local
223 phy_base = ioremap(param->phy[phy].base, SZ_4K); in reg_dump()
226 phy, ptr_to_uint(phy_base)); in reg_dump()
259 iounmap(phy_base); in reg_dump()
H A Dumc-pro4.c135 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
147 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
151 ddrphy_prepare_training(phy_base, phy); in umc_ch_init()
152 ret = ddrphy_training(phy_base); in umc_ch_init()
156 phy_base += 0x00001000; in umc_ch_init()
H A Dumc-ld4.c148 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
157 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
161 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
162 ret = ddrphy_training(phy_base); in umc_ch_init()
H A Dumc-sld8.c151 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
160 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
164 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
165 ret = ddrphy_training(phy_base); in umc_ch_init()
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-inno-usb2.c163 void __iomem *phy_base; member
645 rphy->phy_base = (void __iomem *)dev_read_addr(dev); in rockchip_usb2phy_probe()
646 if (IS_ERR(rphy->phy_base)) { in rockchip_usb2phy_probe()
867 phy_update_bits(rphy->phy_base + 0x30, GENMASK(2, 0), 0x07); in rv1103b_usb2phy_tuning()
870 phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x01 << 3)); in rv1103b_usb2phy_tuning()
873 phy_update_bits(rphy->phy_base + 0x64, GENMASK(6, 3), (0x00 << 3)); in rv1103b_usb2phy_tuning()
876 phy_clear_bits(rphy->phy_base + 0x100, BIT(6)); in rv1103b_usb2phy_tuning()
879 phy_update_bits(rphy->phy_base + 0x11c, GENMASK(4, 0), 0x17); in rv1103b_usb2phy_tuning()
882 phy_update_bits(rphy->phy_base + 0x124, GENMASK(4, 2), (0x03 << 2)); in rv1103b_usb2phy_tuning()
885 phy_update_bits(rphy->phy_base + 0x1a4, GENMASK(7, 4), (0x01 << 4)); in rv1103b_usb2phy_tuning()
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_phy_px30.h55 void phy_soft_reset(void __iomem *phy_base);
56 void phy_dram_set_bw(void __iomem *phy_base, u32 bw);
57 void phy_cfg(void __iomem *phy_base,
60 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);
/rk3399_rockchip-uboot/drivers/usb/host/
H A Dxhci-exynos5.c38 fdt_addr_t phy_base; member
81 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in xhci_usb_ofdata_to_platdata()
82 if (plat->phy_base == FDT_ADDR_T_NONE) { in xhci_usb_ofdata_to_platdata()
213 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base; in xhci_usb_probe()
H A Dehci-exynos.c31 fdt_addr_t phy_base; member
72 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in ehci_usb_ofdata_to_platdata()
73 if (plat->phy_base == FDT_ADDR_T_NONE) { in ehci_usb_ofdata_to_platdata()
221 ctx->usb = (struct exynos_usb_phy *)plat->phy_base; in ehci_usb_probe()