Lines Matching refs:phy_base
566 void __iomem *phy_base = dram->phy; in phy_pll_set() local
571 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); in phy_pll_set()
572 while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) { in phy_pll_set()
596 writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); in phy_pll_set()
597 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, in phy_pll_set()
599 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, in phy_pll_set()
602 clrsetbits_le32(PHY_REG(phy_base, 0x52), in phy_pll_set()
604 clrsetbits_le32(PHY_REG(phy_base, 0x53), in phy_pll_set()
886 void __iomem *phy_base = dram->phy; in set_ds_odt() local
1043 clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); in set_ds_odt()
1044 clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv); in set_ds_odt()
1045 clrsetbits_le32(PHY_REG(phy_base, 0x102), 0x1f, phy_clk_drv); in set_ds_odt()
1046 clrsetbits_le32(PHY_REG(phy_base, 0x103), 0x1f, phy_clk_drv); in set_ds_odt()
1048 clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_clk_drv); in set_ds_odt()
1049 clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_clk_drv); in set_ds_odt()
1051 clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_ca_drv); in set_ds_odt()
1052 clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_ca_drv); in set_ds_odt()
1055 clrsetbits_le32(PHY_REG(phy_base, 0x106), 0x1f, sr_clk); in set_ds_odt()
1065 clrsetbits_le32(PHY_REG(phy_base, j + 1), 0x1f, phy_odt_up); in set_ds_odt()
1066 clrsetbits_le32(PHY_REG(phy_base, j), 0x1f, phy_odt_dn); in set_ds_odt()
1067 clrsetbits_le32(PHY_REG(phy_base, j + 2), 0x1f, phy_dq_drv); in set_ds_odt()
1068 clrsetbits_le32(PHY_REG(phy_base, j + 3), 0x1f, phy_dq_drv); in set_ds_odt()
1069 writel(vref_inner, PHY_REG(phy_base, 0x118 + i * 0x10)); in set_ds_odt()
1071 clrsetbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), in set_ds_odt()
1074 clrbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), BIT(5)); in set_ds_odt()
1076 clrsetbits_le32(PHY_REG(phy_base, 0x117 + i * 0x10), in set_ds_odt()
1081 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in set_ds_odt()
1082 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in set_ds_odt()
1085 writel(vref_out, PHY_REG(phy_base, 0x105)); in set_ds_odt()
1227 void __iomem *phy_base = dram->phy; in sdram_cmd_dq_path_remap() local
1242 PHY_REG(phy_base, 0x4f)); in sdram_cmd_dq_path_remap()
1251 void __iomem *phy_base = dram->phy; in phy_cfg() local
1260 phy_base + sdram_params->phy_regs.phy[i][0]); in phy_cfg()
1263 clrbits_le32(PHY_REG(phy_base, 0x62), BIT(5)); in phy_cfg()
1264 dq_map = readl(PHY_REG(phy_base, 0x4f)); in phy_cfg()
1278 tmp = readl(PHY_REG(phy_base, 0xf)) & (~PHY_DQ_WIDTH_MASK); in phy_cfg()
1286 writel(tmp, PHY_REG(phy_base, 0xf)); in phy_cfg()
1291 clrsetbits_le32(PHY_REG(phy_base, 0x20), 0x7 << 4, in phy_cfg()
1294 setbits_le32(PHY_REG(phy_base, 0x1e), BIT(6)); in phy_cfg()
1295 setbits_le32(PHY_REG(phy_base, 0x1f), BIT(6)); in phy_cfg()
1297 clrbits_le32(PHY_REG(phy_base, 0x7c), BIT(5)); in phy_cfg()
1372 void __iomem *phy_base = dram->phy; in record_dq_prebit() local
1377 writel(dq_sel[i][0], PHY_REG(phy_base, in record_dq_prebit()
1379 tmp = readl(PHY_REG(phy_base, grp_addr[group] + 0x2e)); in record_dq_prebit()
1380 writel(tmp, PHY_REG(phy_base, in record_dq_prebit()
1384 writel(dq_sel[i][0], PHY_REG(phy_base, in record_dq_prebit()
1386 tmp = readl(PHY_REG(phy_base, grp_addr[group] + 0x2f)); in record_dq_prebit()
1387 writel(tmp, PHY_REG(phy_base, in record_dq_prebit()
1395 void __iomem *phy_base = dram->phy; in update_dq_rx_prebit() local
1397 clrsetbits_le32(PHY_REG(phy_base, 0x70), BIT(1) | BIT(6) | BIT(4), in update_dq_rx_prebit()
1400 clrbits_le32(PHY_REG(phy_base, 0x70), BIT(4)); in update_dq_rx_prebit()
1405 void __iomem *phy_base = dram->phy; in update_dq_tx_prebit() local
1407 clrbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); in update_dq_tx_prebit()
1408 setbits_le32(PHY_REG(phy_base, 0x2), BIT(3)); in update_dq_tx_prebit()
1409 setbits_le32(PHY_REG(phy_base, 0xc), BIT(6)); in update_dq_tx_prebit()
1411 clrbits_le32(PHY_REG(phy_base, 0xc), BIT(6)); in update_dq_tx_prebit()
1416 void __iomem *phy_base = dram->phy; in update_ca_prebit() local
1418 clrbits_le32(PHY_REG(phy_base, 0x25), BIT(2)); in update_ca_prebit()
1419 setbits_le32(PHY_REG(phy_base, 0x22), BIT(6)); in update_ca_prebit()
1421 clrbits_le32(PHY_REG(phy_base, 0x22), BIT(6)); in update_ca_prebit()
1433 void __iomem *phy_base = dram->phy; in modify_ca_deskew() local
1445 ((readl(PHY_REG(phy_base, 0x60)) & BIT(5)) == 0)) { in modify_ca_deskew()
1447 setbits_le32(PHY_REG(phy_base, 0x60), BIT(5)); in modify_ca_deskew()
1455 tmp = readl(PHY_REG(phy_base, 0x150 + i)) + in modify_ca_deskew()
1457 writel(tmp, PHY_REG(phy_base, 0x150 + i)); in modify_ca_deskew()
1463 tmp = readl(PHY_REG(phy_base, 0x150 + 0x17)) - in modify_ca_deskew()
1465 writel(tmp, PHY_REG(phy_base, 0x150 + 0x17)); in modify_ca_deskew()
1466 writel(tmp, PHY_REG(phy_base, 0x150 + 0x18)); in modify_ca_deskew()
1468 writel(tmp, PHY_REG(phy_base, 0x150 + 0x4)); in modify_ca_deskew()
1469 writel(tmp, PHY_REG(phy_base, 0x150 + 0xa)); in modify_ca_deskew()
1471 clrbits_le32(PHY_REG(phy_base, 0x10), cs_en << 6); in modify_ca_deskew()
1477 clrbits_le32(PHY_REG(phy_base, 0x60), BIT(5)); in modify_ca_deskew()
1485 void __iomem *phy_base = dram->phy; in get_min_value() local
1493 min = MIN(min, readl(PHY_REG(phy_base, 0x150 + i))); in get_min_value()
1495 byte_en = readl(PHY_REG(phy_base, 0xf)) & 0xf; in get_min_value()
1501 readl(PHY_REG(phy_base, in get_min_value()
1535 void __iomem *phy_base = dram->phy; in modify_dq_deskew() local
1539 byte_en = readl(PHY_REG(phy_base, 0xf)) & 0xf; in modify_dq_deskew()
1553 tmp = delta_sig + readl(PHY_REG(phy_base, in modify_dq_deskew()
1556 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + i)); in modify_dq_deskew()
1561 tmp = delta_dif + readl(PHY_REG(phy_base, in modify_dq_deskew()
1563 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + 9)); in modify_dq_deskew()
1564 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + 0xa)); in modify_dq_deskew()
1574 void __iomem *phy_base = dram->phy; in data_training_rg() local
1584 odt_val_dn = readl(PHY_REG(phy_base, 0x110)); in data_training_rg()
1585 odt_val_up = readl(PHY_REG(phy_base, 0x111)); in data_training_rg()
1591 PHY_REG(phy_base, j)); in data_training_rg()
1593 PHY_REG(phy_base, j + 0x1)); in data_training_rg()
1598 clrbits_le32(PHY_REG(phy_base, 0xc), BIT(1)); in data_training_rg()
1602 setbits_le32(PHY_REG(phy_base, 0xc), BIT(1)); in data_training_rg()
1611 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs)); in data_training_rg()
1613 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1); in data_training_rg()
1615 ret = readl(PHY_REG(phy_base, 0x91)); in data_training_rg()
1617 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0); in data_training_rg()
1618 clrbits_le32(PHY_REG(phy_base, 2), 0x30); in data_training_rg()
1627 ret = (ret & 0x2f) ^ (readl(PHY_REG(phy_base, 0xf)) & 0xf); in data_training_rg()
1632 writel(odt_val_dn, PHY_REG(phy_base, j)); in data_training_rg()
1633 writel(odt_val_up, PHY_REG(phy_base, j + 0x1)); in data_training_rg()
1643 void __iomem *phy_base = dram->phy; in data_training_wl() local
1651 clrbits_le32(PHY_REG(phy_base, 0x7a), 0x1); in data_training_wl()
1656 writel(tmp & 0xff, PHY_REG(phy_base, 0x3)); in data_training_wl()
1663 writel(0x40 | ((tmp >> 8) & 0x3f), PHY_REG(phy_base, 0x4)); in data_training_wl()
1665 writel(0x80 | ((tmp >> 8) & 0x3f), PHY_REG(phy_base, 0x4)); in data_training_wl()
1668 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), in data_training_wl()
1671 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), in data_training_wl()
1675 if ((readl(PHY_REG(phy_base, 0x92)) & 0xf) == in data_training_wl()
1676 (readl(PHY_REG(phy_base, 0xf)) & 0xf)) in data_training_wl()
1688 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), in data_training_wl()
1690 clrsetbits_le32(PHY_REG(phy_base, 2), 0x3 << 6, 0 << 6); in data_training_wl()
1713 void __iomem *phy_base = dram->phy; in data_training_rd() local
1725 vref_inner = readl(PHY_REG(phy_base, 0x128)) & 0xff; in data_training_rd()
1729 PHY_REG(phy_base, 0x118 + i * 0x10)); in data_training_rd()
1732 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in data_training_rd()
1733 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in data_training_rd()
1752 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff); in data_training_rd()
1753 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f); in data_training_rd()
1755 clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x); in data_training_rd()
1757 clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4); in data_training_rd()
1760 clrsetbits_le32(PHY_REG(phy_base, 0x71), 0x3 << 6, (0x2 >> cs) << 6); in data_training_rd()
1764 setbits_le32(PHY_REG(phy_base, 0x70), BIT(7)); in data_training_rd()
1768 PHY_REG(phy_base, 0x238 + i)); in data_training_rd()
1771 PHY_REG(phy_base, 0x2b8 + i)); in data_training_rd()
1776 clrsetbits_le32(PHY_REG(phy_base, 0x230), 0x3f, dqs_default); in data_training_rd()
1778 clrsetbits_le32(PHY_REG(phy_base, 0x234), 0x3f, dqs_default); in data_training_rd()
1780 clrsetbits_le32(PHY_REG(phy_base, 0x2b0), 0x3f, dqs_default); in data_training_rd()
1782 clrsetbits_le32(PHY_REG(phy_base, 0x2b4), 0x3f, dqs_default); in data_training_rd()
1785 clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x1); in data_training_rd()
1787 clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x3); in data_training_rd()
1791 if ((readl(PHY_REG(phy_base, 0x93)) >> 7) & 0x1) in data_training_rd()
1802 if ((readl(PHY_REG(phy_base, 0x240)) & 0x3) || in data_training_rd()
1803 (readl(PHY_REG(phy_base, 0x2c0)) & 0x3)) { in data_training_rd()
1809 clrbits_le32(PHY_REG(phy_base, 0x70), BIT(1)); in data_training_rd()
1816 PHY_REG(phy_base, 0x118 + i * 0x10)); in data_training_rd()
1819 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in data_training_rd()
1820 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in data_training_rd()
1830 void __iomem *phy_base = dram->phy; in data_training_wr() local
1838 phy_fsp = (readl(PHY_REG(phy_base, 0xc)) >> 0x2) & 0x3; in data_training_wr()
1840 cl = readl(PHY_REG(phy_base, offset)); in data_training_wr()
1841 cwl = readl(PHY_REG(phy_base, offset + 2)); in data_training_wr()
1843 clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, 0x8); in data_training_wr()
1844 clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, 0x4); in data_training_wr()
1851 clrsetbits_le32(PHY_REG(phy_base, 0x7b), 0xff, 0x0); in data_training_wr()
1853 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x7 << 2, 0x0 << 2); in data_training_wr()
1855 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3, 0x0); in data_training_wr()
1857 clrsetbits_le32(PHY_REG(phy_base, 0x7d), 0xff, 0x0); in data_training_wr()
1859 clrsetbits_le32(PHY_REG(phy_base, 0x7e), 0xff, 0x0); in data_training_wr()
1862 clrbits_le32(PHY_REG(phy_base, 0x71), BIT(3)); in data_training_wr()
1871 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff); in data_training_wr()
1872 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f); in data_training_wr()
1874 clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x); in data_training_wr()
1876 clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4); in data_training_wr()
1879 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3 << 6, (0x2 >> cs) << 6); in data_training_wr()
1884 setbits_le32(PHY_REG(phy_base, 0x7a), BIT(4)); in data_training_wr()
1887 setbits_le32(PHY_REG(phy_base, 0x7a), 0x1); in data_training_wr()
1890 setbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); in data_training_wr()
1895 if ((readl(PHY_REG(phy_base, 0x92)) >> 7) & 0x1) in data_training_wr()
1907 if ((readl(PHY_REG(phy_base, 0x90)) >> 5) & 0x7) { in data_training_wr()
1913 clrbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); in data_training_wr()
1920 ((readl(PHY_REG(phy_base, 0x384)) & 0x3f) + in data_training_wr()
1921 (readl(PHY_REG(phy_base, 0x385)) & 0x3f)) / 2; in data_training_wr()
1924 ((readl(PHY_REG(phy_base, 0x7c)) & BIT(5)) << 1); in data_training_wr()
1928 clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, cl); in data_training_wr()
1929 clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, cwl); in data_training_wr()
1988 void __iomem *phy_base = dram->phy; in get_wrlvl_val() local
2005 (readl(PHY_REG(phy_base, wrlvl_result_offset[j][i])) & 0x3f) - in get_wrlvl_val()
2015 void __iomem *phy_base, u8 cs_num) in init_rw_trn_result_struct() argument
2026 static void save_rw_trn_min_max(void __iomem *phy_base, in save_rw_trn_min_max() argument
2045 readb(PHY_REG(phy_base, phy_ofs + 0x15 + dq)); in save_rw_trn_min_max()
2047 readb(PHY_REG(phy_base, phy_ofs + 0x27 + dq)); in save_rw_trn_min_max()
2049 readb(PHY_REG(phy_base, phy_ofs + 0x3d + dq)); in save_rw_trn_min_max()
2051 readb(PHY_REG(phy_base, phy_ofs + 0x4f + dq)); in save_rw_trn_min_max()
2056 static void save_rw_trn_deskew(void __iomem *phy_base, in save_rw_trn_deskew() argument
2071 readb(PHY_REG(phy_base, phy_ofs + dq)); in save_rw_trn_deskew()
2073 readb(PHY_REG(phy_base, phy_ofs + 0xb + dq)); in save_rw_trn_deskew()
2075 readb(PHY_REG(phy_base, phy_ofs + 0x60 + dq)); in save_rw_trn_deskew()
2077 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0xb + dq)); in save_rw_trn_deskew()
2081 readb(PHY_REG(phy_base, phy_ofs + 0x8)); in save_rw_trn_deskew()
2083 readb(PHY_REG(phy_base, phy_ofs + 0xb + 0x8)); in save_rw_trn_deskew()
2085 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0x8)); in save_rw_trn_deskew()
2087 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0xb + 0x8)); in save_rw_trn_deskew()
2103 void __iomem *phy_base = dram->phy; in high_freq_training() local
2110 byte_en = readl(PHY_REG(phy_base, 0xf)) & PHY_DQ_WIDTH_MASK; in high_freq_training()
2147 writel(wrlvl_result[0][0] + clk_skew, PHY_REG(phy_base, 0x233)); in high_freq_training()
2148 writel(wrlvl_result[0][1] + clk_skew, PHY_REG(phy_base, 0x237)); in high_freq_training()
2149 writel(wrlvl_result[0][2] + clk_skew, PHY_REG(phy_base, 0x2b3)); in high_freq_training()
2150 writel(wrlvl_result[0][3] + clk_skew, PHY_REG(phy_base, 0x2b7)); in high_freq_training()
2155 save_rw_trn_min_max(phy_base, &rw_trn_result.rd_fsp[fsp].cs[0], in high_freq_training()
2160 writel(wrlvl_result[1][0] + clk_skew, PHY_REG(phy_base, 0x233)); in high_freq_training()
2161 writel(wrlvl_result[1][1] + clk_skew, PHY_REG(phy_base, 0x237)); in high_freq_training()
2162 writel(wrlvl_result[1][2] + clk_skew, PHY_REG(phy_base, 0x2b3)); in high_freq_training()
2163 writel(wrlvl_result[1][3] + clk_skew, PHY_REG(phy_base, 0x2b7)); in high_freq_training()
2168 save_rw_trn_min_max(phy_base, &rw_trn_result.rd_fsp[fsp].cs[1], in high_freq_training()
2183 save_rw_trn_deskew(phy_base, &rw_trn_result.rd_fsp[fsp], in high_freq_training()
2200 save_rw_trn_deskew(phy_base, &rw_trn_result.wr_fsp[fsp], in high_freq_training()
2570 void __iomem *phy_base = dram->phy; in sdram_init_() local
2657 setbits_le32(PHY_REG(phy_base, 0xf), 0xf); in sdram_init_()
2698 ddr4_vref = readl(PHY_REG(phy_base, 0x105)) * 39; in sdram_init_()
2715 void __iomem *phy_base = dram->phy; in dram_detect_cap() local
2794 setbits_le32(PHY_REG(phy_base, 0xf), 0xf); in dram_detect_cap()
2800 dq_map = readl(PHY_REG(phy_base, 0x4f)); in dram_detect_cap()
2807 clrsetbits_le32(PHY_REG(phy_base, 0xf), PHY_DQ_WIDTH_MASK, in dram_detect_cap()
3016 void __iomem *phy_base = dram->phy; in pre_set_rate() local
3060 phy_base + phy_offset + in pre_set_rate()
3080 PHY_REG(phy_base, 0x1b)); in pre_set_rate()
3087 PHY_REG(phy_base, 0x19)); in pre_set_rate()
3097 PHY_REG(phy_base, 0x17)); in pre_set_rate()
3102 PHY_REG(phy_base, 0x18)); in pre_set_rate()
3111 PHY_REG(phy_base, 0x1a)); in pre_set_rate()
3124 PHY_REG(phy_base, 0x1d)); in pre_set_rate()
3130 PHY_REG(phy_base, 0x1c)); in pre_set_rate()
3140 void __iomem *phy_base = dram->phy; in save_fsp_param() local
3161 p_fsp_param->rd_odt = readl(PHY_REG(phy_base, 0x111)); in save_fsp_param()
3163 p_fsp_param->rd_odt = readl(PHY_REG(phy_base, 0x110)); in save_fsp_param()
3166 p_fsp_param->wr_dq_drv = readl(PHY_REG(phy_base, 0x112)); in save_fsp_param()
3167 p_fsp_param->wr_ca_drv = readl(PHY_REG(phy_base, 0x100)); in save_fsp_param()
3168 p_fsp_param->wr_ckcs_drv = readl(PHY_REG(phy_base, 0x102)); in save_fsp_param()
3169 p_fsp_param->vref_inner = readl(PHY_REG(phy_base, 0x128)); in save_fsp_param()
3170 p_fsp_param->vref_out = readl(PHY_REG(phy_base, 0x105)); in save_fsp_param()
3207 temp = MAX(readl(PHY_REG(phy_base, 0x3ae)), in save_fsp_param()
3208 readl(PHY_REG(phy_base, 0x3ce))); in save_fsp_param()
3209 temp1 = MIN(readl(PHY_REG(phy_base, 0x3be)), in save_fsp_param()
3210 readl(PHY_REG(phy_base, 0x3de))); in save_fsp_param()
3212 temp = MAX(readl(PHY_REG(phy_base, 0x3af)), in save_fsp_param()
3213 readl(PHY_REG(phy_base, 0x3cf))); in save_fsp_param()
3214 temp1 = MIN(readl(PHY_REG(phy_base, 0x3bf)), in save_fsp_param()
3215 readl(PHY_REG(phy_base, 0x3df))); in save_fsp_param()
3218 (readl(PHY_REG(phy_base, 0x1e)) & BIT(6)); in save_fsp_param()
3220 (readl(PHY_REG(phy_base, 0x1e)) & BIT(6)); in save_fsp_param()
3222 p_fsp_param->lp4_drv_pd_en = (readl(PHY_REG(phy_base, 0x114)) >> in save_fsp_param()
3391 void __iomem *phy_base = dram->phy; in ddr_set_rate() local
3465 clrbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET); in ddr_set_rate()
3469 setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET); in ddr_set_rate()
3495 clrsetbits_le32(PHY_REG(phy_base, 0xc), 0x3 << 2, dst_fsp << 2); in ddr_set_rate()
3499 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in ddr_set_rate()
3500 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in ddr_set_rate()