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Searched refs:phase (Results 1 – 25 of 31) sorted by relevance

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/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
109 phase = (reg >> REG_PHY_PHASE_OFFS) & in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
113 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
114 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
115 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
116 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
182 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
291 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
293 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
[all …]
H A Dddr3_write_leveling.c67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
118 phase = in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
187 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
344 phase = in ddr3_wl_supplement()
352 [P] = phase; in ddr3_wl_supplement()
362 phase, delay); in ddr3_wl_supplement()
365 phase = in ddr3_wl_supplement()
374 if ((phase == 0) in ddr3_wl_supplement()
375 || ((phase == 1) in ddr3_wl_supplement()
[all …]
H A Dddr3_hw_training.c548 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay) in ddr3_write_pup_reg() argument
558 reg |= (phase << REG_PHY_PHASE_OFFS) | delay; in ddr3_write_pup_reg()
1049 u32 pup, reg, phase; in ddr3_get_min_max_rl_phase() local
1056 phase = ((reg >> 8) & 0x7); in ddr3_get_min_max_rl_phase()
1058 if (phase < *min) in ddr3_get_min_max_rl_phase()
1059 *min = phase; in ddr3_get_min_max_rl_phase()
1061 if (phase > *max) in ddr3_get_min_max_rl_phase()
1062 *max = phase; in ddr3_get_min_max_rl_phase()
H A Dddr3_hw_training.h327 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
/rk3399_rockchip-uboot/drivers/usb/emul/
H A Dsandbox_flash.c61 enum cmd_phase phase; member
295 priv->phase = priv->transfer_len ? PHASE_DATA : PHASE_STATUS; in handle_ufi_command()
308 dev->name, pipe, ep, len, priv->phase); in sandbox_flash_bulk()
311 switch (priv->phase) { in sandbox_flash_bulk()
334 switch (priv->phase) { in sandbox_flash_bulk()
346 priv->phase = PHASE_STATUS; in sandbox_flash_bulk()
351 priv->phase = PHASE_STATUS; in sandbox_flash_bulk()
359 priv->phase = PHASE_START; in sandbox_flash_bulk()
/rk3399_rockchip-uboot/include/
H A Dsym53c8xx.h526 #define WHEN(phase) (0x00030000 | (phase)) argument
527 #define IF(phase) (0x00020000 | (phase)) argument
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1563 int phase, adll; in ddr3_tip_wl_supp_one_clk_err_shift() local
1570 phase = ((data >> 6) & 0x7); in ddr3_tip_wl_supp_one_clk_err_shift()
1574 if_id, bus_id, phase, adll)); in ddr3_tip_wl_supp_one_clk_err_shift()
1576 if ((phase == 0) || (phase == 1)) { in ddr3_tip_wl_supp_one_clk_err_shift()
1579 DDR_PHY_DATA, 0, (phase + 2), 0x1f)); in ddr3_tip_wl_supp_one_clk_err_shift()
1580 } else if (phase == 2) { in ddr3_tip_wl_supp_one_clk_err_shift()
1606 int phase, adll; in ddr3_tip_wl_supp_align_err_shift() local
1613 phase = ((data >> 6) & 0x7); in ddr3_tip_wl_supp_align_err_shift()
1618 if_id, bus_id, phase, adll)); in ddr3_tip_wl_supp_align_err_shift()
1620 if (phase < 2) { in ddr3_tip_wl_supp_align_err_shift()
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H A Dddr3_training_static.c156 u32 phase = 0; in ddr3_tip_write_leveling_static_config() local
172 phase = round_trip_delay_arr[bus_index] / (32 * adll_period); in ddr3_tip_write_leveling_static_config()
174 (phase * 32 * adll_period)) / adll_period; in ddr3_tip_write_leveling_static_config()
183 bus_index, phase, adll)); in ddr3_tip_write_leveling_static_config()
192 ((phase << 6) + (adll & 0x1f)), 0x1df)); in ddr3_tip_write_leveling_static_config()
/rk3399_rockchip-uboot/arch/x86/include/asm/fsp/
H A Dfsp_api.h58 enum fsp_phase phase; member
H A Dfsp_support.h77 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c134 static void mctl_enable_dll0(u32 phase) in mctl_enable_dll0() argument
139 ((phase >> 16) & 0x3f) << 6); in mctl_enable_dll0()
164 static void mctl_enable_dllx(u32 phase) in mctl_enable_dllx() argument
173 (phase & 0xf) << 14); in mctl_enable_dllx()
176 phase >>= 4; in mctl_enable_dllx()
H A DKconfig329 the delay on the command lane and also phase shifts, which are
331 means that no phase/delay adjustments are necessary. Properly
682 int "LCD panel display clock phase"
686 Select LCD panel display clock phase shift, range 0-3.
/rk3399_rockchip-uboot/drivers/nvme/
H A Dnvme.c185 u16 phase = nvmeq->cq_phase; in nvme_submit_sync_cmd() local
197 if ((status & 0x01) == phase) in nvme_submit_sync_cmd()
207 status, phase, head); in nvme_submit_sync_cmd()
211 phase = !phase; in nvme_submit_sync_cmd()
215 nvmeq->cq_phase = phase; in nvme_submit_sync_cmd()
225 phase = !phase; in nvme_submit_sync_cmd()
229 nvmeq->cq_phase = phase; in nvme_submit_sync_cmd()
/rk3399_rockchip-uboot/arch/x86/lib/fsp/
H A Dfsp_support.c185 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) in fsp_notify() argument
201 params.phase = phase; in fsp_notify()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3036-sdk-u-boot.dtsi11 default-sample-phase = <0>;
H A Drk3128-u-boot.dtsi49 default-sample-phase = <0>;
/rk3399_rockchip-uboot/doc/
H A DREADME.android-fastboot-protocol41 d. DATA -> the requested command is ready for the data phase.
46 3. Data phase. Depending on the command, the host or client will
48 acceptable and zero-length packets are ignored. This phase continues
H A DREADME.srio-pcie-boot-corenet72 startup phase of the slave from SRIO or PCIE, it will finish some
/rk3399_rockchip-uboot/drivers/ddr/altera/
H A Dsequencer.c286 static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase) in scc_mgr_set_dqdqs_output_phase() argument
288 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase); in scc_mgr_set_dqdqs_output_phase()
296 static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase) in scc_mgr_set_dqs_en_phase() argument
298 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase); in scc_mgr_set_dqs_en_phase()
392 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) in scc_mgr_set_dqs_en_phase_all_ranks() argument
403 read_group, phase, 0); in scc_mgr_set_dqs_en_phase_all_ranks()
407 u32 phase) in scc_mgr_set_dqdqs_output_phase_all_ranks() argument
418 write_group, phase, 0); in scc_mgr_set_dqdqs_output_phase_all_ranks()
2533 const u32 phase) in rw_mgr_mem_calibrate_guaranteed_write() argument
2538 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase); in rw_mgr_mem_calibrate_guaranteed_write()
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/exynos/
H A Ddwmmc.txt36 . The above 3 values are used by the clock phase shifter.
/rk3399_rockchip-uboot/board/keymile/km83xx/
H A DREADME.kmeter17 phase it might be helpful to apply an alternative boot configuration in
/rk3399_rockchip-uboot/examples/standalone/
H A DREADME_rkspi.md64 #define SPI_CPHA BIT(0) /* clock phase */
/rk3399_rockchip-uboot/drivers/power/regulator/
H A DKconfig212 LP87565 series of PMICs have 4 single phase BUCKs that can also
213 be configured in multi phase modes. The driver implements
/rk3399_rockchip-uboot/doc/device-tree-bindings/spi/
H A Dspi-bus.txt53 shifted clock phase (CPHA) mode
/rk3399_rockchip-uboot/drivers/net/
H A Dmvpp2.c3630 enum mv_netc_phase phase) in gop_netc_mac_to_xgmii() argument
3632 switch (phase) { in gop_netc_mac_to_xgmii()
3648 enum mv_netc_phase phase) in gop_netc_mac_to_sgmii() argument
3650 switch (phase) { in gop_netc_mac_to_sgmii()
3673 static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase) in gop_netc_init() argument
3678 gop_netc_mac_to_sgmii(priv, 2, phase); in gop_netc_init()
3680 gop_netc_mac_to_xgmii(priv, 2, phase); in gop_netc_init()
3683 gop_netc_mac_to_sgmii(priv, 3, phase); in gop_netc_init()
3685 gop_netc_mac_to_xgmii(priv, 3, phase); in gop_netc_init()
3697 if (phase == MV_NETC_SECOND_PHASE) { in gop_netc_init()

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