nvme: add quirks support

Change-Id: Ieeb3d993967973c160c477b3d833f6e27de31d26
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

nvme: Add write_zeroes support

Change-Id: I0c7256af24e5e5fa0ec351738ae2509c88114947
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

UPSTREAM: nvme: Update nvme_scan_namespace to keep trying on busy

A busy controller shouldn't be game-over for all controllers,
so keep trying on hitting -EBUSY.

This change brings the actual behav

UPSTREAM: nvme: Update nvme_scan_namespace to keep trying on busy

A busy controller shouldn't be game-over for all controllers,
so keep trying on hitting -EBUSY.

This change brings the actual behavior of the routine in line
with what the descriptions says.

Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Moritz Fischer <moritzf@google.com>
[Fix some merge error]
Change-Id: I803c95f6dd464c3cfba278f29309c1e86039b52f
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

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UPSTREAM: nvme: Fix error code and log to indicate busy

Return -EBUSY if controller is found busy rather than -ENOMEM
and update the error message accordingly.

Change-Id: I263f2e90d7a4288913cd65978

UPSTREAM: nvme: Fix error code and log to indicate busy

Return -EBUSY if controller is found busy rather than -ENOMEM
and update the error message accordingly.

Change-Id: I263f2e90d7a4288913cd65978baf0ef636ffcec1
Fixes: 982388eaa991 ("nvme: Add NVM Express driver support")
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

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nvme: add erase support

Use discard to erase the desired LBA

[1]
=> md.l 0x44000000 0x200 #先读一下0x44000000的内存地址
44000000: 00000000 00000000 20014080 00000200 .........@. ....
44000010: 440044

nvme: add erase support

Use discard to erase the desired LBA

[1]
=> md.l 0x44000000 0x200 #先读一下0x44000000的内存地址
44000000: 00000000 00000000 20014080 00000200 .........@. ....
44000010: 44004400 02010108 00002000 24000200 .D.D..... .....$
44000020: 08801000 10000000 00000000 80008018 ................

[2]
=> nvme read 0x44000000 0x0 1 #NVMe LBA 0读一个block到0x44000000

nvme read: device 0 block # 0, count 1 ... 1 blocks read: OK

[3]
=> md.l 0x44000000 0x200 #再读一下0x44000000的内存地址，变了
44000000: 4a400000 00000001 17c00000 00000002 ..@J............
44000010: 4aa00000 00000001 16700000 00000002 ...J......p.....

[4]
=> nvme erase 0x0 0x1 #0地址开始，擦除一个block

nvme erase: device 0 block # 0, count 1 ... 1 blocks erased: OK

[5]
=> nvme read 0x44000000 0x0 1 #再从NVMe的LBA 0地址读一个block数据到0x44000000

nvme read: device 0 block # 0, count 1 ... 1 blocks read: OK

[6]
=> md.l 0x44000000 0x200 #NVMe第一个block的数据已经清除了
44000000: 00000000 00000000 00000000 00000000 ................
44000010: 00000000 00000000 00000000 00000000 ................
44000020: 00000000 00000000 00000000 00000000 ................
...

Change-Id: I0495b3538acbfb1e522b027a635b74a078ccab15
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

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nvme: Support bounce buffer for cache coherent

Change-Id: Id834f059d0222d6c0ec31724d27c81aba0fc4a82
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

UPSTREAM: nvme: invalidate correct memory range after read

The current code invalidates the range after the read buffer since the
buffer pointer gets incremented in the read loop. Use a temporary
po

UPSTREAM: nvme: invalidate correct memory range after read

The current code invalidates the range after the read buffer since the
buffer pointer gets incremented in the read loop. Use a temporary
pointer to make sure we have a pristine pointer to invalidate the
correct memory range after read.

Fixes: 704e040a51d2 ("nvme: Apply cache operations on the DMA buffers")
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Change-Id: I330a49e28c54d068a285d4a56f1c62b2bc8e06a6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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nvme: Fix error in nvme_setup_prps

Consulting to "NVM Express® Base Specification, revision 2.0".

If more PRP List pages are required, then the last entry of
the PRP List contains the Page Base Add

nvme: Fix error in nvme_setup_prps

Consulting to "NVM Express® Base Specification, revision 2.0".

If more PRP List pages are required, then the last entry of
the PRP List contains the Page Base Address of the next PRP
List page. The next PRP List page shall be memory page aligned.

Change-Id: Iea14d1fdd56dcd7674565d29b827c242301a0600
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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nvme: Enable FUA

Most NVME devcies maintain data in internal cache for an uncertain
times, and u-boot has no method to force NVME to flush cache.
So this patch adds FUA to avoid data loss caused by

nvme: Enable FUA

Most NVME devcies maintain data in internal cache for an uncertain
times, and u-boot has no method to force NVME to flush cache.
So this patch adds FUA to avoid data loss caused by power off after data
programming.

Change-Id: Ic581ec99f46b6dfa2e0b1922e670a333ac859e82
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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UPSTREAM: nvme: Don't clear nvme blk device's priv space

A udevice's priv space is cleared in alloc_priv() in the DM core.
Don't do it again in its probe() routine.

Change-Id: Ia11053d05522db13add3

UPSTREAM: nvme: Don't clear nvme blk device's priv space

A udevice's priv space is cleared in alloc_priv() in the DM core.
Don't do it again in its probe() routine.

Change-Id: Ia11053d05522db13add372e7deb32d5a465496eb
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 78d5f2011e2acf8e2f259d2886f1ceb4d789e0be)

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UPSTREAM: nvme: Drop useless members of 'struct nvme_ns'

mode_select_num_blocks and mode_select_block_len in 'struct nvme_ns'
are not useful. Drop them.

Change-Id: I2e2b2ffdf630d51654db3698e0c7c3a2

UPSTREAM: nvme: Drop useless members of 'struct nvme_ns'

mode_select_num_blocks and mode_select_block_len in 'struct nvme_ns'
are not useful. Drop them.

Change-Id: I2e2b2ffdf630d51654db3698e0c7c3a21edfd2f2
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 757cc4b1b2725e445a94840aa6076f0f0d4f03b9)

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UPSTREAM: nvme: Eliminate the offset of one during block dev creation

At present there is an offset of one added during the creation of
block device. This can be very confusing as we wanted to encod

UPSTREAM: nvme: Eliminate the offset of one during block dev creation

At present there is an offset of one added during the creation of
block device. This can be very confusing as we wanted to encode the
namespace id in the block device name but namespae id cannot be zero.

This changes to use the namespace id directly in the block device
name, eliminating the offset of one effectively.

Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Change-Id: I80d9bee9338ab5495e770ac7feb8df4fa425e434
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8c60d40d69fd834f67322bbcea06ef0adf9076e1)

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UPSTREAM: nvme: Skip block device creation for inactive namespaces

At present for each namespace there is a block device created for it.
There is no issue if the number of supported namespaces repor

UPSTREAM: nvme: Skip block device creation for inactive namespaces

At present for each namespace there is a block device created for it.
There is no issue if the number of supported namespaces reported from
the NVMe device is only 1.

Since QEMU commit 7f0f1acedf15 ("hw/block/nvme: support multiple namespaces"),
the number of supported namespaces reported has been changed from 1
to 256, but not all of them are active namespaces. The actual active
one depends on the QEMU command line parameters. A common case is
that namespace 1 being active and all other 255 being inactive.

If a namespace is inactive, the namespace identify command returns a
zero filled data structure. We can use field NSZE (namespace size) to
decide whether a block device should be created for it.

Change-Id: I764b2179c3c23ad115429fe4a2f8b6714fc4014d
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 478f7fc6a04ae81af550b56b31f18af24cf3f262)

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UPSTREAM: nvme: Move block dev creation from uclass post_probe() to driver probe()

At present the block device creation happens in the NVMe uclass
driver post_probe() phase. In preparation to suppor

UPSTREAM: nvme: Move block dev creation from uclass post_probe() to driver probe()

At present the block device creation happens in the NVMe uclass
driver post_probe() phase. In preparation to support multiple
namespaces, we should issue namespace identify before creating
block devices but that touches the underlying hardware hence it
is not appropriate to do such in the uclass driver post_probe().
Let's move it to driver probe() phase instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
(cherry picked from commit 84344258f23fb9ac5abe7383c909f8606ac767b6)
Change-Id: I1e7b1e499982355a47ea4c2de301c6885f551c36

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UPSTREAM: nvme: Remove the redundant aqa value setting

AQA (Admin Queue Attributes) register is a dword size with
lower word of ASQS, and higher word of ACQS.

The code set the variable aqa twice, b

UPSTREAM: nvme: Remove the redundant aqa value setting

AQA (Admin Queue Attributes) register is a dword size with
lower word of ASQS, and higher word of ACQS.

The code set the variable aqa twice, but it is redundant.

Change-Id: Iccf2cccb3604dc55e4092b56bf22095297f69479
Signed-off-by: Wesley Sheng <wesleyshenggit@sina.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c3e52c71bb0e7e5e34fadafbfcc34bce9899c100)

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UPSTREAM: nvme: Correct the prps per page calculation method

Each prp is 8 bytes, calculate the number of prps
per page should just divide page size by 8
there is no need to minus 1

Change-Id: Ic2e

UPSTREAM: nvme: Correct the prps per page calculation method

Each prp is 8 bytes, calculate the number of prps
per page should just divide page size by 8
there is no need to minus 1

Change-Id: Ic2e9bf861e8eef5418d540e2ca599c890dd0d6d0
Signed-off-by: Wesley Sheng <wesleyshenggit@sina.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 859b33c948945f7904f60a2c12a3792d356d51ad)

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UPSTREAM: nvme: fix for big endian systems

writel() and co. already include the endian swap; doing the swap twice
is, er, unhelpful.

Tested on a P4080DS, which boots perfectly fine off NVMe with t

UPSTREAM: nvme: fix for big endian systems

writel() and co. already include the endian swap; doing the swap twice
is, er, unhelpful.

Tested on a P4080DS, which boots perfectly fine off NVMe with this.

Change-Id: Id6a90e1ac4749d116e0f78eef526956fcc790252
Signed-off-by: David Lamparter <equinox@diac24.net>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b12f62374e83675bc65174c2b4b7e3c6c368aa78)

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UPSTREAM: nvme: Elaborate on cache maintenance operation in get/set_features

At the moment the nvme_get_features() and nvme_set_features() functions
carry a (somewhat misleading) comment about missi

UPSTREAM: nvme: Elaborate on cache maintenance operation in get/set_features

At the moment the nvme_get_features() and nvme_set_features() functions
carry a (somewhat misleading) comment about missing cache maintenance.

As it turns out, nvme_get_features() has no caller at all in the tree,
and nvme_set_features' only user doesn't use a DMA buffer.

Mention that in the comment, and leave some breadcrumbs for the future,
should those functions attract more users.

Change-Id: Ice9717cb8adf0046ff54301b88e9e674dd576220
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4c498796891a26a7283130f367a346096a6ccce7)

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UPSTREAM: nvme: Always invalidate whole cqes[] array

At the moment nvme_read_completion_status() tries to invalidate a single
member of the cqes[] array, which is shady as just a single entry is
not

UPSTREAM: nvme: Always invalidate whole cqes[] array

At the moment nvme_read_completion_status() tries to invalidate a single
member of the cqes[] array, which is shady as just a single entry is
not cache line aligned.
The structure is dictated by hardware, and with 16 bytes is smaller than
any cache line we usually deal with. Also multiple entries need to be
consecutive in memory, so we can't pad them to cover a whole cache line.

As a consequence we can only always invalidate all of them - U-Boot just
uses two of them anyway. This is fine, as they are only ever read by the
CPU (apart from the initial zeroing), so they can't become dirty.

Make this obvious by always invalidating the whole array, regardless of
the entry number we are about to read.
Also blow up the allocation size to cover whole cache lines, to avoid
other heap allocations to sneak in.

Change-Id: Ic904dec7a3b0717fc68084e63dd431f8d4125dbd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d0c04926cd054cf7360ec15913ac17a465f32603)

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UPSTREAM: nvme: Invalidate dcache before submitting admin cmd

This patch try to avoids eviction of dirty lines during DMA
transfer. The code right now execute the following step:

- allocate the buf

UPSTREAM: nvme: Invalidate dcache before submitting admin cmd

This patch try to avoids eviction of dirty lines during DMA
transfer. The code right now execute the following step:

- allocate the buffer
- start a dma operation using the non-coherent dma buffer
- invalidate cache lines associated with the buffer
- read the buffer

This can lead to reading back not valid information, because the cache
controller could evict dirty cache lines belonging to the buffer *after*
the DMA operation has started to fill the DRAM.
In order to avoid this, a new invalidation is required *before* starting
the DMA operation. The patch just adds an invalidation before submitting
the DMA command.

Example below shows the nvme disk scan result without the following
patch

=> nvme scan
nvme_get_info_from_identify: nn = 544502629, vwc = 100,
sn = dev_0T, mn = `�\�, fr = t_part, mdts = 105

So, invalidating the cache before submitting the admin command,
fix the cpu read.

Cc: André Przywara <andre.przywara@arm.com>
Change-Id: Ib38e7ef860cb86a210eefe187720d98d354af7fe
Reported-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 1a027a90aaa65ea429a55035f0316eadd0d83180)

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UPSTREAM: nvme: use page-aligned buffer for identify command

Change the stack-allocated buffer for the identification command
to explicitly allocate page-aligned buffers. Even though the spec
seems

UPSTREAM: nvme: use page-aligned buffer for identify command

Change the stack-allocated buffer for the identification command
to explicitly allocate page-aligned buffers. Even though the spec
seems to allow having admin queue commands on non page-aligned
buffers, it seems to not be possible on my i.MX8MQ board with a
a Silicon Power P34A80. Since all of the NVMe drivers I have seen
always do admin commands on a page-aligned buffer, which does work
on my system, it makes sense for us to do that as well.

Change-Id: I4e73559a6b9d36903f9cc4e687649779c615c063
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2f83481dff9c4f253a6ac341911d78d4984ca07b)

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UPSTREAM: nvme: flush dcache on both r/w, and the prp list

It's possible that the data cache for the buffer still holds data
to be flushed to memory, since the buffer was probably used as stack
befo

UPSTREAM: nvme: flush dcache on both r/w, and the prp list

It's possible that the data cache for the buffer still holds data
to be flushed to memory, since the buffer was probably used as stack
before. Thus we need to make sure to flush it also on reads, since
it's possible that the cache is automatically flused to memory after
the NVMe DMA transfer happened, thus overwriting the NVMe transfer's
data. Also add a missing dcache flush for the prp list.

Change-Id: I40572099e5583e3b155b8b248079b76c8bbd1e5c
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8c403402ca691c967516481b6bc2c879d683a73d)

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UPSTREAM: nvme: add accessor to namespace id and eui64

This adds a function which can be used by e.g. EFI to retrieve
the namespace identifier and EUI64. For that it adds the EUI64
to its driver in

UPSTREAM: nvme: add accessor to namespace id and eui64

This adds a function which can be used by e.g. EFI to retrieve
the namespace identifier and EUI64. For that it adds the EUI64
to its driver internal namespace structure and copies the EUI64
during namespace identification.

Change-Id: I9ba01dbd7de1928e2e72aeaa37be534524d9035c
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c50b2883dfc1ce355dc37238741ef97cd2c5d000)

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UPSTREAM: nvme: Fix PRP Offset Invalid

When large writes take place I saw a Samsung EVO 970+ return a status
value of 0x13, PRP Offset Invalid. I tracked this down to the
improper handling of PRP e

UPSTREAM: nvme: Fix PRP Offset Invalid

When large writes take place I saw a Samsung EVO 970+ return a status
value of 0x13, PRP Offset Invalid. I tracked this down to the
improper handling of PRP entries. The blocks the PRP entries are
placed in cannot cross a page boundary and thus should be allocated
on page boundaries. This is how the Linux kernel driver works.

With this patch, the PRP pool is allocated on a page boundary and
other than the very first allocation, the pool size is a multiple of
the page size. Each page can hold (4096 / 8) - 1 entries since the
last entry must point to the next page in the pool.

Change-Id: I3b22c0b7cc943f196c843559876dc9ebdfad5907
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b21dcebfa6b372cd91bf42a30f1d8a1a525f329b)

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UPSTREAM: nvme: Fix warning of cast from pointer to integer of different size

When dma_addr_t is u32 in 64-bit, there are some warnings when
building NVME driver. Fix it by doing an additional (long

UPSTREAM: nvme: Fix warning of cast from pointer to integer of different size

When dma_addr_t is u32 in 64-bit, there are some warnings when
building NVME driver. Fix it by doing an additional (long) cast.

Change-Id: I45e2004c4904cc3b41530675e869e05994bc6890
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5b2a20e9564c46a571126275991426dd8618e2d8)

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