Lines Matching refs:phase
1563 int phase, adll; in ddr3_tip_wl_supp_one_clk_err_shift() local
1570 phase = ((data >> 6) & 0x7); in ddr3_tip_wl_supp_one_clk_err_shift()
1574 if_id, bus_id, phase, adll)); in ddr3_tip_wl_supp_one_clk_err_shift()
1576 if ((phase == 0) || (phase == 1)) { in ddr3_tip_wl_supp_one_clk_err_shift()
1579 DDR_PHY_DATA, 0, (phase + 2), 0x1f)); in ddr3_tip_wl_supp_one_clk_err_shift()
1580 } else if (phase == 2) { in ddr3_tip_wl_supp_one_clk_err_shift()
1606 int phase, adll; in ddr3_tip_wl_supp_align_err_shift() local
1613 phase = ((data >> 6) & 0x7); in ddr3_tip_wl_supp_align_err_shift()
1618 if_id, bus_id, phase, adll)); in ddr3_tip_wl_supp_align_err_shift()
1620 if (phase < 2) { in ddr3_tip_wl_supp_align_err_shift()
1622 if (phase == 0) in ddr3_tip_wl_supp_align_err_shift()
1625 if (phase == 1) { in ddr3_tip_wl_supp_align_err_shift()
1641 } else if ((phase == 2) || (phase == 3)) { in ddr3_tip_wl_supp_align_err_shift()
1642 phase = phase - 2; in ddr3_tip_wl_supp_align_err_shift()
1643 data = (phase << 6) + (adll & 0x1f); in ddr3_tip_wl_supp_align_err_shift()