Lines Matching refs:phase
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
118 phase = in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
187 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
344 phase = in ddr3_wl_supplement()
352 [P] = phase; in ddr3_wl_supplement()
362 phase, delay); in ddr3_wl_supplement()
365 phase = in ddr3_wl_supplement()
374 if ((phase == 0) in ddr3_wl_supplement()
375 || ((phase == 1) in ddr3_wl_supplement()
381 phase = 0x0; in ddr3_wl_supplement()
385 [P] = phase; in ddr3_wl_supplement()
393 phase, delay); in ddr3_wl_supplement()
438 phase = in ddr3_wl_supplement()
441 if (phase > dram_info->wl_max_phase) in ddr3_wl_supplement()
442 dram_info->wl_max_phase = phase; in ddr3_wl_supplement()
443 if (phase < dram_info->wl_min_phase) in ddr3_wl_supplement()
444 dram_info->wl_min_phase = phase; in ddr3_wl_supplement()
475 u32 reg, phase, delay, cs, pup, pup_num; in ddr3_write_leveling_hw_reg_dimm() local
541 phase = in ddr3_write_leveling_hw_reg_dimm()
545 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw_reg_dimm()
547 if ((phase == 1) && (delay >= 0x1D)) { in ddr3_write_leveling_hw_reg_dimm()
1128 u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup, in ddr3_write_leveling_single_cs() local
1222 for (phase = 0; phase < phaseMax; phase++) { in ddr3_write_leveling_single_cs()
1225 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, phase, in ddr3_write_leveling_single_cs()
1231 DEBUG_WL_FULL_D((u32) phase, 1); in ddr3_write_leveling_single_cs()
1269 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_single_cs()
1293 phase = phaseMax; in ddr3_write_leveling_single_cs()
1322 phase = dram_info->wl_val[cs][pup][P]; in ddr3_write_leveling_single_cs()
1324 ddr3_write_pup_reg(PUP_WL_MODE, cs, pup_num, phase, delay); in ddr3_write_leveling_single_cs()