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Searched refs:para (Results 1 – 18 of 18) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a33.c33 static void mctl_set_cr(struct dram_para *para) in mctl_set_cr() argument
38 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
40 (para->seq ? MCTL_CR_SEQUENCE : 0) | in mctl_set_cr()
41 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
42 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
43 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
47 static void auto_detect_dram_size(struct dram_para *para) in auto_detect_dram_size() argument
49 u8 orig_rank = para->rank; in auto_detect_dram_size()
53 para->page_size = 512; in auto_detect_dram_size()
54 para->seq = 1; in auto_detect_dram_size()
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H A Ddram_sun8i_a83t.c32 static void mctl_set_cr(struct dram_para *para) in mctl_set_cr() argument
37 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
38 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | in mctl_set_cr()
39 (para->seq ? MCTL_CR_SEQUENCE : 0) | in mctl_set_cr()
40 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
41 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
42 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
46 static void auto_detect_dram_size(struct dram_para *para) in auto_detect_dram_size() argument
48 u8 orig_rank = para->rank; in auto_detect_dram_size()
52 para->page_size = 512; in auto_detect_dram_size()
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H A Ddram_sun9i.c341 static void mctl_com_init(struct dram_sun9i_para *para) in mctl_com_init() argument
347 writel(((para->chan == 2) ? MCTL_CR_CHANNEL_DUAL : in mctl_com_init()
350 | MCTL_CR_ROW(para->rows) in mctl_com_init()
351 | ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) in mctl_com_init()
352 | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_RANK(para->rank), in mctl_com_init()
358 static u32 mctl_channel_init(u32 ch_index, struct dram_sun9i_para *para) in mctl_channel_init() argument
378 const u32 tREFI = NS2CYCLES_FLOOR(para->tREFI); in mctl_channel_init()
379 const u32 tRFC = NS2CYCLES_ROUNDUP(para->tRFC); in mctl_channel_init()
380 const u32 tRCD = PS2CYCLES_ROUNDUP(para->tRCD); in mctl_channel_init()
381 const u32 tRP = PS2CYCLES_ROUNDUP(para->tRP); in mctl_channel_init()
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H A Ddram_sunxi_dw.c28 static void mctl_set_bit_delays(struct dram_para *para) in mctl_set_bit_delays() argument
38 writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) | in mctl_set_bit_delays()
39 DXBDLR_READ_DELAY(para->dx_read_delays[i][j]), in mctl_set_bit_delays()
43 writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]), in mctl_set_bit_delays()
268 static void mctl_h3_zq_calibration_quirk(struct dram_para *para) in mctl_h3_zq_calibration_quirk() argument
335 static void mctl_set_cr(uint16_t socid, struct dram_para *para) in mctl_set_cr() argument
350 (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | in mctl_set_cr()
351 MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | in mctl_set_cr()
352 (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | in mctl_set_cr()
353 MCTL_CR_PAGE_SIZE(para->page_size) | in mctl_set_cr()
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H A Ddram_sun4i.c562 static unsigned long dramc_init_helper(struct dram_para *para) in dramc_init_helper() argument
573 if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1) in dramc_init_helper()
577 mctl_setup_dram_clock(para->clock, para->mbus_clock); in dramc_init_helper()
593 mctl_enable_dll0(para->tpr3); in dramc_init_helper()
597 reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3); in dramc_init_helper()
599 if (para->density == 256) in dramc_init_helper()
601 else if (para->density == 512) in dramc_init_helper()
603 else if (para->density == 1024) in dramc_init_helper()
605 else if (para->density == 2048) in dramc_init_helper()
607 else if (para->density == 4096) in dramc_init_helper()
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H A Ddram_sun6i.c52 static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para) in mctl_dll_init() argument
65 if (para->bus_width == 32) { in mctl_dll_init()
75 if (para->bus_width == 32) { in mctl_dll_init()
85 if (para->bus_width == 32) { in mctl_dll_init()
103 static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para) in mctl_channel_init() argument
167 para->rank = 1; in mctl_channel_init()
176 para->chan = 1; in mctl_channel_init()
183 para->bus_width = 16; in mctl_channel_init()
184 para->page_size = 2048; in mctl_channel_init()
244 if (para->bus_width == 16) in mctl_channel_init()
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/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_px30.c586 ddr_param->para[0] = 0; in get_ddr_param()
587 ddr_param->para[1] = cs_cap[0] * 4 / 3; in get_ddr_param()
588 ddr_param->para[2] = cs_cap[0]; in get_ddr_param()
589 ddr_param->para[3] = cs_cap[1]; in get_ddr_param()
592 ddr_param->para[0] = 0; in get_ddr_param()
593 ddr_param->para[1] = (u64)cs_cap[0] + (u64)cs_cap[1]; in get_ddr_param()
H A Dsdram_rv1108.c223 ddr_param->para[0] = CONFIG_SYS_SDRAM_BASE; in get_ddr_param()
224 ddr_param->para[1] = ram_size; in get_ddr_param()
H A Dsdram_rk3328.c600 ddr_parem.para[0] = priv->info.base; in rk3328_dmc_probe()
601 ddr_parem.para[1] = priv->info.size; in rk3328_dmc_probe()
H A Dsdram_rv1108_pctl_phy.c605 ddr_param.para[0] = priv->info.base; in sdram_all_config()
606 ddr_param.para[1] = priv->info.size; in sdram_all_config()
H A Dsdram_rk3399.c3179 ddr_parem.para[0] = priv->info.base; in rk3399_dmc_probe()
3180 ddr_parem.para[1] = priv->info.size; in rk3399_dmc_probe()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h26 u64 para[8]; member
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dsdram.c211 dinfo->para[i] = info->para[i]; in rockchip_setup_ddr_param()
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/dram_timings/
H A Dddr3_1333.c5 void mctl_set_timing_params(uint16_t socid, struct dram_para *para) in mctl_set_timing_params() argument
H A Dlpddr3_stock.c5 void mctl_set_timing_params(uint16_t socid, struct dram_para *para) in mctl_set_timing_params() argument
H A Dddr2_v3s.c5 void mctl_set_timing_params(uint16_t socid, struct dram_para *para) in mctl_set_timing_params() argument
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun4i.h179 unsigned long dramc_init(struct dram_para *para);
H A Ddram_sunxi_dw.h237 void mctl_set_timing_params(uint16_t socid, struct dram_para *para);