| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3066.c | 57 u32 nf; member
96 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
113 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
117 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
128 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
131 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
145 {.nf = 25, .nr = 2, .no = 1}, in rkclk_configure_ddr()
146 {.nf = 400, .nr = 9, .no = 2}, in rkclk_configure_ddr()
147 {.nf = 500, .nr = 9, .no = 2}, in rkclk_configure_ddr()
148 {.nf = 100, .nr = 3, .no = 1}, in rkclk_configure_ddr()
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| H A D | clk_rk3188.c | 58 u32 nf; member
94 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
111 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
115 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
126 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
129 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
143 {.nf = 25, .nr = 2, .no = 1}, in rkclk_configure_ddr()
144 {.nf = 400, .nr = 9, .no = 2}, in rkclk_configure_ddr()
145 {.nf = 500, .nr = 9, .no = 2}, in rkclk_configure_ddr()
146 {.nf = 100, .nr = 3, .no = 1}, in rkclk_configure_ddr()
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| H A D | clk_rk3288.c | 37 u32 nf; member
46 .nf = _nf, \
213 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
241 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
245 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
252 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
258 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
272 u32 nr, no, nf; in rkclk_pll_get_rate() local
293 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; in rkclk_pll_get_rate()
295 return (24 * nf / (nr * no)) * 1000000; in rkclk_pll_get_rate()
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| H A D | clk_rk3368.c | 34 u32 nf; member
43 .nf = _nf, \
107 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
144 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; in pll_para_config() local
166 div->nf = best_div->nf; in pll_para_config()
196 nf = vco_khz / fref_khz; in pll_para_config()
197 if (nf >= max_nf) in pll_para_config()
199 diff_khz = vco_khz - nf * fref_khz; in pll_para_config()
200 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { in pll_para_config()
201 nf++; in pll_para_config()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 92 unsigned int nf; member
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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip-inno-hdmi-phy.c | 894 u16 nf; in inno_hdmi_3328_phy_pll_recalc_rate() local
897 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); in inno_hdmi_3328_phy_pll_recalc_rate()
898 vco = parent_rate * nf; in inno_hdmi_3328_phy_pll_recalc_rate()
1103 u16 nf; in inno_hdmi_rk3528_phy_pll_recalc_rate() local
1107 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1108 vco *= nf; in inno_hdmi_rk3528_phy_pll_recalc_rate()
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